Christine Wallace
Altis Semiconductor
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Publication
Featured researches published by Christine Wallace.
Metrology, inspection, and process control for microlothoggraphy. Conference | 2001
Graham G. Arthur; Brian Martin; Christine Wallace
The optimization of a dielectric anti-reflective coating (ARC) on a transparent substrate with significant topography is described. Supporting theory is provided and although it is not possible to obtain the ultimate performance of an ARC over planar film stacks and flat substrates, the critical dimension (CD) swing ratio is greatly reduced and a manufactureable solution achieved using response surface modeling (RSM) in combination with data generated form the lithography simulation tool, PROLITH/2.
18th Annual BACUS Symposium on Photomask Technology and Management | 1998
Graham G. Arthur; Brian Martin; Christine Wallace; Anja Rosenbusch; Huw Fryer
The application of Optical Proximity Correction for improving uniformity of printed dimensions at sub-half-micron resolution in a 0.35 micron CMOS process is described. Results are presented in terms of measurements made on polysilicon gates, at different pitches, which are compared to the uncorrected case. The impact of photomask and stepper lens qualities on dimensional control are also considered. Results presented are at the demonstrator stage but strategy for implementation in production is discussed.
Metrology, inspection, and process control for microlithography. Conference | 2000
Christine Wallace; Brian Martin; Graham G. Arthur
The variation of dimensional control between center and edge of a stepper lens field is measured both practically and by lithography simulation for both lines and slots at various pitches. Results for lines show that the sign of the center- edge offset is pitch dependent but for slots the dimension is always larger at center field irrespective of pitch.
Metrology, inspection, and process control for microlithography. Conference | 2000
Christine Wallace; Claire Duncan; Brian Martin
Optical proximity correction in terms of linewidth correction at different pitches is used to demonstrate improvement in critical dimension control at the polysilicon layer of a sub- half-micron CMOS process. Further measurements across the image field show the effect on wafer linewidth distributions of different generations of the laser write tool used in reticle manufacturing.
Metrology, inspection, and process control for microlithography. Conference | 2000
Graham G. Arthur; Brian Martin; Christine Wallace
A production application of optical proximity correction (OPC) aimed at reducing corner-rounding and line-end shortening is described. The methodology, using critical shape error analysis, to calculate the correct serif size is given and is extended to show the effect of OPC on the process window (i.e. depth-of-focus and exposure latitude). The initial calculations are made using the lithography simulation tools PROLITH/2 and SOLID-C, the results of which are transferred to the photo-cell for practical results.
Lithography for semiconductor manufacturing. Conference | 1999
Christine Wallace; Brian Martin; Graham G. Arthur
Resist contrast is related to usable depth-of-focus (UDOF) for I-line and DUV stepper lenses through the resists process linearity function. Results, supported by simulations in the resist image, show that stepper field center-edge critical dimensional offsets, which decrease UDOF, increase as resist contrast decreases. Measurements on intra-field CDs show that their uniformity decreases as processes reach non-linear processing regimes.
Metrology, inspection, and process control for microlithography. Conference | 1998
Brian Martin; Graham G. Arthur; Christine Wallace
This paper investigates photoresist profiles on low reflectivity substrates with respect to numerical aperture and position in lens field. Results suggest a link between resist wall angle and substrate reflectivity which is influenced by lens aberrations.
Metrology, inspection, and process control for microlithography. Conference | 1998
Christine Wallace; Brian Martin; Graham G. Arthur
Control of contact hole sizes in a sub-half-micron CMOS process using planarisation by resist etch back and chemical mechanical polishing is discussed. The limitations of using top anti-reflective coatings to overcome thin film effects on transparent substrates are calculated by simulation. Use of bottom anti-reflective coatings to improve uniformity in the resist etch back process are described through practical results which additionally show that comparable results are achieved in the chemical mechanical polishing process but in the absence of a bottom anti-reflective coating.
Metrology, inspection, and process control for microlithography. Conference | 1998
Graham G. Arthur; Christine Wallace; Brian Martin
Archive | 2001
Brian Martin; Christine Wallace