Christoforos Kachris

Optical interconnection networks in data centers: recent trends and future challenges

Warehouse-scale data center operators need much-higher-bandwidth intra-data center networks (DCNs) to sustain the increase of network traffic due to cloud computing and other emerging web applications. Current DCNs based on commodity switches require excessive amounts of power to face this traffic increase. Optical intra-DCN interconnection networks have recently emerged as a promising solution that can provide higher throughput while consuming less power. This article provides an update on recent developments in the field of ultra-highcapacity optical interconnects for intra-DCN communication. Several recently proposed architectures and technologies are examined and compared, while future trends and research challenges are outlined.

Optical Interconnects for Future Data Center Networks

Optical Interconnects in Future Data Center Networks covers optical networks and how they can be used to provide high bandwidth, energy efficient interconnects for future data centers with increased communication bandwidth requirements. This contributed volume presents an integrated view of the future requirements of the data centers and serves as a reference work for some of the most advanced solutions that have been proposed by major universities and companies. Collecting the most recent and innovative optical interconnects for data center networks that have been presented in the research community by universities and industries, this book is a valuable reference to researchers, students, professors and engineers interested in the domain of high performance interconnects and data center networks. Additionally, Optical Interconnects in Future Data Center Networks provides invaluable insights into the benefits and advantages of optical interconnects and how they can be a promising alternative for future data center networks.

A Survey on FEC Codes for 100 G and Beyond Optical Networks

Due to the rapid increase in network traffic in the last few years, many telecommunication operators have started transitions to 100-Gb/s optical networks and beyond. However, high-speed optical networks need more efficient forward error correction (FEC) codes to deal with optical impairments, such as uncompensated chromatic dispersion, polarization mode dispersion, and nonlinear effects, and keep the bit error rate (BER) at long distances sufficiently low. To address these issues, new FEC codes, called third-generation codes, have been proposed. A majority of these codes are based on soft-decision decoders and can provide higher coding gain as compared with their predecessors. This paper presents a thorough survey of third-generation FEC codes, suitable for 100 G and beyond optical networks. Furthermore, this paper discusses the main advantages and drawbacks of each scheme and provides a qualitative categorization and comparison of the proposed schemes based on their main features, such as net coding gain and BER. Information about the complexity of each scheme is given as well.

Analysis of a reconfigurable network processor

In this paper an analysis of a dynamically reconfigurable processor is presented. The network processor incorporates a processor and a number of coprocessors that can be connected to the processor either directly or using a shared bus. The analysis investigates the configuration (in terms of co-processor distributions and interface), formulates the throughput that meets the network demands and the constraints of the platform (area, bus bandwidth, etc.) and takes into account the reconfiguration overhead. To find the configuration that meets the constraints, the platform is formulated into integer linear programming equations. Furthermore, the results of two case studies are presented, for a soft- and a hard-IP core processor, that uses three flows with different processing requirements (IP forward, encryption and media processing). In each case the number and the type of co-processors is shown in terms of the network distribution and the average packet size. Finally, the mapping of the framework in the Xilinx FPGA platform is discussed

ImpBench: A novel benchmark suite for biomedical, microelectronic implants

So far, design and deployment of microelectronic, implantable devices has largely had a strongly ldquoad-hocrdquo character. The majority of existing devices has been custom-tailored to the specific application in mind, in an effort to abide by strict design constraints on safety as well as power and size. However, an enabling technology and the fact that implants are gradually becoming mainstream market products calls for a more structured design approach. Towards that end, in this paper we present ImpBench, a novel benchmark suite meant for designing and evaluating new digital processors for microelectronic implants. In an application field as wide as the various pathoses of the human body, we have conceptualized this suite based on common-sense and market-driven indicators, and we have established its usefulness and uniqueness based on extensive experimental measurement. The suite consists of eight carefully selected programs, chosen on the basis of popularity among contemporary and emerging implant applications. MiBench being the closest to our application field, that is embedded systems, has been used for a detailed comparative study. Since implants are required to perform control-, processing- or I/O-intensive tasks, various benchmark characteristics have been studied, namely: performance (IPC), cache and branch-prediction behavior, instruction distribution and power consumption. Results display significant variation from existing benchmarks to justify the need for and usefulness of ImpBench.

Performance Evaluation of an Adaptive FPGA for Network Applications

This paper presents the design and the performance evaluation of a coarse-grain dynamically reconfigurable platform for network applications. The platform consists of two MicroBlaze RISC processors and a number of hardware co-processors used for the processing of the packets payload (DES encryption and Lempel-Ziv Compression). The co-processors can be connected either directly to the processors or using a shared bus. The type of the co-processors is dynamically reconfigured to meet the requirements of the network workload. The system has been implemented in the Xilinx Virtex II Pro FPGA platform and the network traces from real passive measurements have been used for performance evaluation. The use of dynamically reconfigurable co-processors for network applications shows that the performance speedup versus a static version varies from 12% to 35% in the best case and from 10% to 15% on average, depending on the variability in time and distribution of the network traffic

A survey on reconfigurable accelerators for cloud computing

Data centers are experiencing an exponential increase in the amount of network traffic that they have to sustain due to cloud computing and several emerging web applications. To face this network load, large data centers are required with thousands of servers interconnected with high bandwidth switches. Current data center, based on general purpose processor, consume excessive power while their utilization is quite low. Hardware accelerators can provide high energy efficiency for many cloud applications but they lack the programming efficiency of processors. In the last few years, there several efforts for the efficient deployment of hardware accelerators in the data centers. This paper presents a thorough survey of the frameworks for the efficient utilization of the FPGAs in the data centers. Furthermore it presents the hardware accelerators that have been implemented for the most widely used cloud computing applications. Furthermore, the paper provides a qualitative categorization and comparison of the proposed schemes based on their main features such as speedup and energy efficiency.

High-performance switching based on buffered crossbar fabrics

As buffer-less crossbar scheduling algorithms reach their practical limitations due to higher port numbers and data rates, internally buffered crossbar (IBC) switches have gained a lot of interest recently due to their great potential in solving the complexity and scalability issues faced by their buffer-less predecessors. The IBC switching architecture combined with the virtual output queueing (VOQ) architecture was shown, through distributed scheduling algorithms, to be able to sustain the current and expected increases in Internet throughput rates. Due to the architectural similarity between the input queued (IQ) and IBC switches, all the algorithms proposed for the latter were just a simple mapping of earlier algorithms proposed for the former. In this paper, we propose a set of scheduling schemes that are purely advocated for the VOQ/IBC switch architecture. We first address the issue of the internal buffers importance in the arbitration process. We propose a weighted scheduling algorithm, named Critical internal Buffer First (CBF), which takes full advantage of the internal buffer elements and makes its decision exclusively on the internal buffer information. Second, in order to simplify the scheduling scheme and make it practical, we propose a class of scheduling algorithms, named Current Arrival First-Priority Removal (CAF-PRMV) that use priority levels instead of weights. We argue that the interaction, through the internal buffer element, between the input and output schedulers is very important in designing such practical and highly scalable schemes for the IBC switching architecture. Our hardware implementation, in reconfigurable logic, shows that our CAF-PRMV class of algorithms can sustain a 10 Gbps line speed for a 32 × 32 VOQ/IBC switch.

Cognitive optical network testbed: EU project CHRON [Invited]

The aim of cognition in optical networks is to introduce intelligence into the control plane that allows for autonomous end-to-end performance optimization and minimization of required human intervention, particularly targeted at heterogeneous network scenarios. A cognitive network observes, learns, and makes informed decisions based on its current status and knowledge about past decisions and their results. To test the operation of cognitive algorithms in real time, we created the first operational testbed of a cognitive optical network based on the Cognitive Heterogeneous Reconfigurable Optical Network (CHRON) architecture. In this experiment, an intelligent control plane, enabled by a cognitive decision system (CDS), was successfully combined with a flexible data plane. The testbed was used to test and validate different scenarios, demonstrating benefits obtained by network cognition, particularly lightpath establishment and a teardown scenario, improved failure restoration time, cognitive virtual topology reconfiguration, and a modulation format change.

Design and performance evaluation of an adaptive FPGA for network applications

This paper presents the design, implementation and performance evaluation of a coarse-grain dynamically reconfigurable FPGA platform for multi-service edge and access network devices. The platform consists of two MicroBlaze RISC processors and a number of hardware co-processors used for the processing of packet payloads (Data Encryption Standard (DES) and Lempel-Ziv Compression). The co-processors can be connected either directly to the processors or using a shared bus. The functionality of the co-processors is dynamically reconfigured to meet the requirements of the network workload. The system has been implemented on the Xilinx Virtex II Pro platform and the network traces from real passive measurements have been used for performance evaluation. The use of dynamically reconfigurable co-processors for network applications shows that the performance speedup versus a static version varies from 12% to 35% in the best case and from 10% to 15% on average, depending on the network traffic fluctuation.