Christoph Hohle

Evaluation of an advanced dual hard mask stack for high resolution pattern transfer

A dual hard mask concept for high resolution patterning has been evaluated with focus on highly selective etching processes for semiconductor manufacturing. The integration of thin SiO2 and ZrO2 hard mask materials enables highly selective patterning via plasma etch processes for future technology nodes. The patterning sequence is demonstrated for hole arrays with sizes down to 25 nm using a 50 nm thin resist which leads to the fabrication of trenches in silicon with aspect ratios up to 20:1. Alternative ZrO2 based materials were investigated with focus on surface roughness reduction since it influences the final line etch roughness. Here Si-doped ZrO2 (ALD) and spin-coatable ZrO2 were compared to the pure and crystalline ZrO2 as main selective material.

Verification of E-Beam direct write integration into 28nm BEOL SRAM technology

Electron beam direct write lithography (EBDW) potentially offers advantages for low-volume semiconductor manufacturing, rapid prototyping or design verification due to its high flexibility without the need of costly masks. However, the integration of this advanced patterning technology into complex CMOS manufacturing processes remains challenging. The low throughput of today’s single e-Beam tools limits high volume manufacturing applications and maturity of parallel (multi) beam systems is still insufficient [1,2]. Additional concerns like transistor or material damage of underlying layers during exposure at high electron density or acceleration voltage have to be addressed for advanced technology nodes. In the past we successfully proved that potential degradation effects of high-k materials or ULK shrink can be neglected and were excluded by demonstrating integrated electrical results of 28nm node transistor and BEOL performance following 50kV electron beam dry exposure [3]. Here we will give an update on the integration of EBDW in the 300mm CMOS manufacturing processes of advanced integrated circuits at the 28nm SRAM node of GLOBALFOUNDRIES Dresden. The work is an update to what has been previously published [4]. E-beam patterning results of BEOL full chip metal and via layers with a dual damascene integration scheme using a 50kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer IPMSCNT are demonstrated. For the patterning of the Metal layer a Mix & Match concept based on the sequence litho - etch -litho -etch (LELE) was developed and evaluated wherein several exposure fields were blanked out during the optical exposure. Etch results are shown and compared to the POR. Results are also shown on overlay performance and optimized e-Beam exposure time using most advanced data prep solutions and resist processes. The patterning results have been verified using fully integrated electrical measurement of metal lines and vias on wafer level. In summary we demonstrate the integration capability of EBDW into a productive CMOS process flow at the example of the 28nm SRAM technology node.

Line End Shortening and Application of Novel Correction Algorithms in E-Beam Direct Write

For the manufacturing of semiconductor technologies following the ITRS roadmap, we will face the nodes well below 32nm half pitch in the next 2~3 years. Despite being able to achieve the required resolution, which is now possible with electron beam direct write variable shaped beam (EBDW VSB) equipment and resists, it becomes critical to precisely reproduce dense line space patterns onto a wafer. This exposed pattern must meet the targets from the layout in both dimensions (horizontally and vertically). For instance, the end of a line must be printed in its entire length to allow a later placed contact to be able to land on it. Up to now, the control of printed patterns such as line ends is achieved by a proximity effect correction (PEC) which is mostly based on a dose modulation. This investigation of the line end shortening (LES) includes multiple novel approaches, also containing an additional geometrical correction, to push the limits of the available data preparation algorithms and the measurement. The designed LES test patterns, which aim to characterize the status of LES in a quick and easy way, were exposed and measured at Fraunhofer Center Nanoelectronic Technologies (CNT) using its state of the art electron beam direct writer and CD-SEM. Simulation and exposure results with the novel LES correction algorithms applied to the test pattern and a large production like pattern in the range of our target CDs in dense line space features smaller than 40nm will be shown.

Extreme long range process effects characterization and compensation

Proximity Effects in electron beam lithography impact feature dimensions, pattern fidelity and uniformity. These effects are addressed using a mathematical model representing the radial exposure intensity distribution induced by a point electron source, commonly named as the Point Spread Function (PSF). PSF models are usually employed for predicting and compensating for effects up to 15μm. It is well known that there are also some process related phenomena that impact pattern uniformity that have a longer range, namely CMP effects, fogging, etc. Performing proximity effects corrections can result in lengthy run times as file size and pattern densities continue to increase exponentially per technology node. Running corrections for extreme long range phenomena becomes computational and file size prohibitive. Nevertheless, since extreme long range may reach up several millimeters, and new technology nodes require a high level of precision, a strategy for predicting and compensating these phenomena is crucial. In this paper a set of test patterns are presented in order to verify and calibrate the so called extreme long range effects in the electron beam lithography. Moreover, a strategy to compensate for extreme long range effects based on the pattern density is presented. Since the evaluation is based on a density map instead of the actual patterns, the computational effort is feasible. The proposed method may be performed off-line (in contrast to machine standard in-line correction). The advantage of employing off-line compensation relies on enhancing the employ of dose and/or geometry modulation. This strategy also has the advantage of being completely decoupled from other e-beam writer’s internal corrections (like Fogging Effect Correction - FEC).

Fabrication of MoS2 biosensor to detect lower-concentrated area of biological molecules(Conference Presentation)

Two dimensional layered transition metal dichalcogenides (TMDC) materials have the growing potential to upstage graphene in the next generation of biosensors in detecting lower-concentrated areas of biomolecules. The current gold-standard detection method is the enzyme-linked immunosorbent assay (ELISA), an immunological assay technique that makes use of an enzyme bonded to a particular antibody or antigen. However, this technique is not only bulky, labor-intensive, and time extensive, but more importantly, the ELISA has relatively low detection limits of only 600 femtomolar (fM). In this work, for the first time, we present a novel flexible, sensitive MoS2 (molybdenum disulfide) biosensor, as shown in Figure 1, composed of few-layer of MoS2 as the channel material, and flexible polyimide as the substrate. In order to nano-fabricate this flexible biosensor, we mechanically transferred a few layers of MoS2 onto the flexible substrate polyimide and photolithography to create a patterning on the surface, and as a result, we were able to create a transistor that used MoS2 as its conductance channel. We successfully fabricated this MoS2 biosensor onto a flexible polyimide substrate. Furthermore, the fabricated flexible MoS2 biosensor can be utilized for quantifying the time-dependent reaction kinetics of streptavidin-biotin binding. Figure 2 shows the transfer characteristics of flexible MoS2 biosensors measured under different concentrations of streptavidin. The flexible MoS2 biosensor could illustrate a faster detection time in matters of minutes, and higher sensitivity with detection limits as low as 10 fM. Time versus equilibrium constants will be presented in details.

Front Matter: Volume 9779

This PDF file contains the front matter associated with SPIE Proceedings Volume 9779, including the Title Page, Copyright information, Table of Contents, Introduction, and the Conference Committee listing.

Metasurfaces for colour printing

We present a theoretical analysis and experimental evidences of metasurfaces based on particle resonators that achieve bright-field colour prints. We created pixels that support individual colours, miniaturized and juxtaposed at the optical diffraction limit. Different strategies are followed to offer the flexibility of using both transmitting and epi (reflective) white light sources. We discuss their potential applications in large-volume colour printing via nanoimprint lithography.

Integration of e-beam direct write in BEOL processes of 28nm SRAM technology node using mix and match

Many efforts were spent in the development of EUV technologies, but from a customer point of view EUV is still behind expectations. In parallel since years maskless lithography is included in the ITRS roadmap wherein multi electron beam direct patterning is considered as an alternative or complementary approach for patterning of advanced technology nodes. The process of multi beam exposures can be emulated by single beam technologies available in the field. While variable shape-beam direct writers are already used for niche applications, the integration capability of e-beam direct write at advanced nodes has not been proven, yet. In this study the e-beam lithography was implemented in the BEoL processes of the 28nm SRAM technology. Integrated 300mm wafers with a 28nm back-end of line (BEoL) stack from GLOBALFOUNDRIES, Dresden, were used for the experiments. For the patterning of the Metal layer a Mix and Match concept based on the sequence litho - etch - litho – etch (LELE) was developed and evaluated wherein several exposure fields were blanked out during the optical exposure. E-beam patterning results of BEoL Metal and Via layers are presented using a 50kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer IPMS-CNT. Etch results are shown and compared to the POR. In summary we demonstrate the integration capability of EBDW into a productive CMOS process flow at the example of the 28nm SRAM technology node.

High-density capacitors for SiP and SoC applications based on three-dimensional integrated metal-isolator-metal structures

This paper focuses on zirconia and TiN based metal-isolator-metal capacitors integrated in immediate vicinity to the Si substrate. A high capacitance density is aimed by significant area enhancement realized through silicon pattering. By material optimization the capacitors also withstand higher supply voltages and show excellent temperature and reliability performance independently of the 3D structure.

Influence of high-energy electron irradiation on ultra-low-k characteristics and transistor performance

While significant resources are invested in bringing EUV lithography to the market, multi electron beam direct patterning is still being considered as an alternative or complementary approach for patterning of advanced technology nodes. The possible introduction of direct write technology into an advanced process flow however may lead to new challenges. For example, the impact of high-energy electrons on dielectric materials and devices may lead to changes in the electrical parameters of the circuit compared to parts conventionally exposed by optical lithography. Furthermore, degradation of product reliability may occur. These questions have not yet been clarified in detail. For this study, pre-structured 300mm wafers with a 28nm BEOL stack were dry-exposed at various processing levels using a 50kV variable shaped e-beam direct writer. The electrical parameters of exposed structures were compared to non-exposed structures. The data of line resistance, capacitance, and line to line leakage were found to be within the typical distributions of the standard process. The dielectric breakdown voltages were also comparable between the splits, suggesting no dramatic TDDB performance degradation. With respect to high-k metal gate transistor parameters, a decrease in threshold voltage shift sensitivity was observed as well as a reduced sensitivity to hot carrier injection. More detailed investigations are needed to determine how these findings need to be considered and whether they represent a risk for the introduction of maskless lithography into the process flow of advanced technology nodes.