Christopher Campbell

Beam angle control on the VIISta 80 ion implanter

Advanced integrated circuit design requires precise control of beam incidence angle. This requirement has led to the development of an automated angle control system on Varian Semiconductors high current VIISta 80 ion implanter. In this paper we show beam incidence angle and angular spread measurements for 200 and 300 mm ion beams on the VIISta 80 ion implanter. Multiple beam measurements are sampled across the wafer plane for each beam setup. Beam angle computation results are compensated for prior to wafer implantation for optimal incident angle control. Beam, bare wafer and device performance data were used to confirm the accuracy of this measurement and control system. Excellent measurement accuracy and repeatability has been demonstrated. Data will be shown which includes arsenic, boron and phosphorus implants from both drift and decel operation. Benefits and process differences will be shown with active beam angle correction as compared to classical open loop methods. Mechanical tilt angle accuracy, repeatability and verification data will also be discussed.

Angle Effects in High Current Ion Implantation

Previous studies conducted on batch high current implanters with 130 nm devices[1] have shown the importance of implant angle during source‐drain (SD) and source‐drain extension (SDE) implants. For these implants, errors in implant angle lead to device asymmetry and this device asymmetry has been cited as a reason for requiring single wafer high current implanters[2]. The sensitivity of device performance to angle is increasing as devices shrink. For current anneal technologies, angle effects are more importance in NMOS, due to the lower diffusion of arsenic. However, the importance of implant angle in PMOS is expected to increase as diffusionless anneals are adopted. In this paper we report on angle effects in single wafer high current ion implantation, for the improvement of the characteristics of MOSFETs integrated into Systems‐on‐a‐Chip (SoCs) of 65 nm or beyond. The single wafer high current implanter and its angle measurement and control system will be described. A comparison of the implanter’s angl...