Christopher J. Terman

A single-chip 1.6 billion 16-b MAC/s multiprocessor DSP

An MIMD multiprocessor digital signal-processing (DSP) chip containing four 64-b processing elements (PEs) interconnected by a 128-b pipelined split transaction bus (STBus) is presented. Each PE contains a 32-b RISC core with DSP enhancements and a 64-b single-instruction, multiple-data vector coprocessor with four 16-b MAC/s and a vector reduction unit. PEs are connected to the STBus through reconfigurable dual-ported snooping L1 cache memories that support shared memory multiprocessing using a modified-MESI data coherency protocol. High-bandwidth data transfers between system memory and on-chip caches are managed in a pipelined memory controller that supports multiple outstanding transactions. An embedded RTOS dynamically schedules multiple tasks onto the PEs. Process synchronization is achieved using cached semaphores. The 200-mm/sup 2/, 0.25-/spl mu/m CMOS chip operates at 100 MHz and dissipates 4 W from a 3.3-V supply.

A video decoder for H.261 video teleconferencing and MPEG stored interactive video applications

A 450-MOPS video decoder that decompresses both H.261 and MPEG (Motion Picture Experts Group) compressed video streams is described. The decoder accepts bit rates up to 4 Mb/s and provides decoded frames of up to 352*288 pixels (CIF) at up to 30 frame/s operating at 45 MHz. The decoder places no restrictions on the H.261 bit streams. It decodes any combination of intra and predictive frames in QCIF or CIF format. In MPEG mode, it decodes any stream conforming to the MPEG constrained parameters, including any combination of intra, predictive, and bidirectional frames with half-pixel motion vectors. The architecture features a mix of dedicated hardware functions and programmable processors. The design methodology used for the decoder included extensive high-level modeling at two levels: a C++ behavioral model and a set of clock-cycle-accurate C models at the block level.<<ETX>>