Christopher T. Clarke

Very Low-Noise ENG Amplifier System Using CMOS Technology

In this paper, we describe the design and testing of a system for recording electroneurographic signals (ENG) from a multielectrode nerve cuff (MEC). This device, which is an extension of the conventional nerve signal recording cuff, enables ENG to be classified by action potential velocity. In addition to electrical measurements, we provide preliminary in vitro data obtained from frogs that demonstrate the validity of the technique for the first time. Since typical ENG signals are extremely small, on the order of 1 1 muV, very low-noise, high-gain amplifiers are required. The ten-channel system we describe was realized in a 0.8 mum CMOS technology and detailed measured results are presented. The overall gain is 10 000 and the total input-referred root mean square (rms) noise in a bandwidth 1 Hz-5 kHZ is 291 nV. The active area is 12 mm2 and the power consumption is 24 mW from plusmn2.5 V power supplies

Selecting Profitable Custom Instructions for Area–Time-Efficient Realization on Reconfigurable Architectures

Profitable custom instructions provide higher performance for a given reconfigurable area. Hence, choosing profitable custom instructions that are also area-time efficient is essential if design constraints must be met by field-programmable-gate-array (FPGA)-based reconfigurable processors. In this paper, we propose a framework for FPGA-based reconfigurable processors in order to rapidly identify a reduced set of profitable custom instructions without the need for actual hardware synthesis. The proposed framework is capable of estimating the area utilization and latencies of custom instructions on lookup-table-based commercial FPGAs. Simulations based on 15 applications from benchmark suites show that the proposed method provides, on average, an area reduction of over 29% for loss of mere 1.3% in compute performance. Our evaluations also confirm that the proposed framework is superior to an existing area-optimization approach that relies on exploiting the regularity of custom instruction data paths. In particular, an average area-time product gain of over 59% was achieved by deploying a reduced set of custom instructions obtained using the proposed framework.

The theory of velocity selective neural recording: a study based on simulation

This paper describes the improvements to the theory of velocity selective recording and some simulation results. In this method, activity in different groups of axons is discriminated by their propagation velocity. A multi-electrode cuff and an array of amplifiers produce multiple neural signals; if artificial delays are inserted and the signals are added, the activity in axons of the matched velocity are emphasized. We call this intrinsic velocity selective recording. However, simulation shows that interpreting the time signals is then not straight-forward and the selectivity Qv is low. New theory shows that bandpass filters improve the selectivity and explains why this is true in the time domain. A simulation study investigates the limits on the available velocity selectivity both with and without additive noise and with reasonable sampling rates and analogue-to-digital conversion parameters. Bandpass filters can improve the selectivity by factors up to 7 but this depends on the speed of the action potential and the signal-to-noise ratio.

Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs

Area-time efficient custom instructions are desirable for maximizing the performance of reconfigurable processors. Existing data path merging techniques based on resource sharing can be deployed to improve area efficiency of custom instructions. However, these techniques lead to large increase in the critical path delay. In this paper, we propose a novel strategy that takes into account the architectural constraints of the FPGA device in order to realize custom instructions with low-area delay product. The proposed strategy is based on partitioning the custom instruction data paths into a set of basic clusters such that they can be combined using a heuristic-based cluster merging process to maximize the utilization of FPGA logic blocks. Unlike the resource sharing method, the proposed cluster merging process does not maximize sharing of common resources and this leads to lesser reliance on multiplexers for implementing custom instructions. Resource sharing is only applied sparingly at the final stage to increase utilization of logic blocks. We show that the proposed technique leads to more than 34 percent, 34 percent, and 42 percent average reduction in area costs for Spartan-3, Virtex-4, and Virtex-5 architectures, respectively, when compared to optimizations achieved through commercial synthesis tool. We have also shown that the proposed technique leads to more than 18 percent, 17 percent, and 13 percent average reduction in area costs for Spartan-3, Virtex-4, and Virtex-5, respectively, when compared to results obtained using one of the most efficient resource sharing-based method reported in the literature. In addition, the proposed technique outperforms the resource sharing-based method in terms of area-delay product, with average reductions of more than 27 percent, 34 percent, and 19 percent for Spartan-3, Virtex-4, and Virtex-5, respectively.

A summary of the theory of velocity selective neural recording

This paper describes improvements to the technique of velocity selective recording (VSR) in which multiple neural signals are matched and summed to identify excited axon populations in terms of velocity. This form of recording has been termed intrinsic velocity selective recording (IVSR). The signals are acquired using a multi-electrode cuff (MEC) which is now available as a component for use in implantable neuroprostheses. The improvements outlined in the paper involve the use of bandpass filters at the output of the system which allows a higher level of selectivity to be obtained than is possible using IVSR.

Profile directed instruction cache tuning for embedded systems

Cache memories improve the performance due to the locality found within the loops of application. Because these loop characteristics are application dependent, the optimal cache hierarchy for performance and energy saving is also application dependent. Traditionally, cache simulations are employed to tune the cache hierarchy. In this paper we propose a simple yet effective loop profiler directed methodology for instruction cache hierarchy optimization. The proposed methodology utilizes the loop characteristics of the application which are readily available from the compiler making it easy to adopt the methodology in an existing design flow.

10-channel very low noise ENG amplifier system using CMOS technology

In this paper the design, fabrication and testing of a 10-channel array of identical amplifiers suitable for velocity selective electroneurogram (ENG) recording is described. The overall gain per channel is 10,000 and the total input-referred rms noise in a bandwidth 1 Hz-5 kHz is 290 nV per channel. The active area is 12 mm/sup 2/ and the power consumption is 24 mW from /spl plusmn/2.5 V power supplies.

A new method for spike extraction using velocity selective recording demonstrated with physiological ENG in Rat

BACKGROUND This paper describes a series of experiments designed to verify a new method of electroneurogram (ENG) recording that enables the rate of neural firing within prescribed bands of propagation velocity to be determined in real time. Velocity selective recording (VSR) has been proposed as a solution to the problem of increasing the information available from an implantable neural interface (typically with electrodes in circumferential nerve cuffs) and has been successful in transforming compound action potentials into the velocity domain. NEW METHOD The new method extends VSR to naturally-evoked (physiological) ENG in which the rate of neural firing at particular velocities is required in addition to a knowledge of the velocities present in the recording. RESULTS The experiments, carried out in rats required individual spikes to be distinct and non-overlapping, which could be achieved by a microchannel or small-bore cuff. In these experiments, strands of rat nerve were laid on ten hook electrodes in oil to demonstrate the principle. COMPARISON WITH EXISTING METHOD The new method generates a detailed overview of the firing rates of neurons based on their conduction velocity and direction of propagation. In addition it allows real time working in contrast to existing spike sorting methods using statistical pattern processing techniques. CONCLUSIONS Results show that by isolating neural activity based purely on conduction velocity it was possible to determine the onset of direct cutaneous stimulation of the L5 dermatome.

An enhancement to velocity selective discrimination of neural recordings: Extraction of neuronal firing rates

This paper describes improvements to the theory of velocity selective recording (VSR) of neural signals. Action potentials are classified and differentiated based on their conduction velocities which can be calculated from concurrent neural recordings taking at different locations on a nerve. Existing work has focussed primarily on electrically evoked compound action potentials (CAPs) where only a single evoked response per velocity is recorded. This paper extends the theory of VSR to naturally occurring neural signals recorded from rat and attempts to identify the level of activity (firing rates) within particular velocity ranges.

Rapid generation of custom instructions using predefined dataflow structures

Abstract Custom instruction generation is fast becoming popular as it provides an alternative means to realize application specific processors. In this paper, we propose an efficient methodology for rapid instruction set customization on RISPs (Reconfigurable Instruction Set Processors) using predefined sets of dataflow structures that are based on templates and reusable structures. A novel template selection strategy was employed to reduce the number of templates required for matching by up to 50%, while providing comparable performance with known approaches. It has been shown that custom instructions could be realized through instantiation of a reduced set of pre-designed reusable structures. Experimental results show that a small number of reusable structures can sufficiently cater to custom instruction generation to notably reduce the time required to realize them on configurable hardware. Moreover, based on our evaluations using MiBench benchmark suites, the reusable structures constitute to only 2% of all the custom instruction instances. The custom instructions generated with reusable structures were implemented in FPGA and it is evident that up to 14% area savings with comparable performance can be achieved when compared with conventional implementation approaches.