Christos Strydis

Cerebellar output controls generalized spike-and-wave discharge occurrence

Disrupting thalamocortical activity patterns has proven to be a promising approach to stop generalized spike‐and‐wave discharges (GSWDs) characteristic of absence seizures. Here, we investigated to what extent modulation of neuronal firing in cerebellar nuclei (CN), which are anatomically in an advantageous position to disrupt cortical oscillations through their innervation of a wide variety of thalamic nuclei, is effective in controlling absence seizures.

Cerebellar control of gait and interlimb coordination

Synaptic and intrinsic processing in Purkinje cells, interneurons and granule cells of the cerebellar cortex have been shown to underlie various relatively simple, single-joint, reflex types of motor learning, including eyeblink conditioning and adaptation of the vestibulo-ocular reflex. However, to what extent these processes contribute to more complex, multi-joint motor behaviors, such as locomotion performance and adaptation during obstacle crossing, is not well understood. Here, we investigated these functions using the Erasmus Ladder in cell-specific mouse mutant lines that suffer from impaired Purkinje cell output (Pcd), Purkinje cell potentiation (L7-Pp2b), molecular layer interneuron output (L7-Δγ2), and granule cell output (α6-Cacna1a). We found that locomotion performance was severely impaired with small steps and long step times in Pcd and L7-Pp2b mice, whereas it was mildly altered in L7-Δγ2 and not significantly affected in α6-Cacna1a mice. Locomotion adaptation triggered by pairing obstacle appearances with preceding tones at fixed time intervals was impaired in all four mouse lines, in that they all showed inaccurate and inconsistent adaptive walking patterns. Furthermore, all mutants exhibited altered front–hind and left–right interlimb coordination during both performance and adaptation, and inconsistent walking stepping patterns while crossing obstacles. Instead, motivation and avoidance behavior were not compromised in any of the mutants during the Erasmus Ladder task. Our findings indicate that cell type-specific abnormalities in cerebellar microcircuitry can translate into pronounced impairments in locomotion performance and adaptation as well as interlimb coordination, highlighting the general role of the cerebellar cortex in spatiotemporal control of complex multi-joint movements.

FPGA-based biophysically-meaningful modeling of olivocerebellar neurons

The Inferior-Olivary nucleus (ION) is a well-charted region of the brain, heavily associated with sensorimotor control of the body. It comprises ION cells with unique properties which facilitate sensory processing and motor-learning skills. Various simulation models of ION-cell networks have been written in an attempt to unravel their mysteries. However, simulations become rapidly intractable when biophysically plausible models and meaningful network sizes (>=100 cells) are modeled. To overcome this problem, in this work we port a highly detailed ION cell network model, originally coded in Matlab, onto an FPGA chip. It was first converted to ANSI C code and extensively profiled. It was, then, translated to HLS C code for the Xilinx Vivado toolflow and various algorithmic and arithmetic optimizations were applied. The design was implemented in a Virtex 7 (XC7VX485T) device and can simulate a 96-cell network at real-time speed, yielding a speedup of x700 compared to the original Matlab code and x12.5 compared to the reference C implementation running on a Intel Xeon 2.66GHz machine with 20GB RAM. For a 1,056-cell network (non-real-time), an FPGA speedup of x45 against the C code can be achieved, demonstrating the designs usefulness in accelerating neuroscience research. Limited by the available on-chip memory, the FPGA can maximally support a 14,400-cell network (non-real-time) with online parameter configurability for cell state and network size. The maximum throughput of the FPGA ION-network accelerator can reach 2.13 GFLOPS.

ImpBench: A novel benchmark suite for biomedical, microelectronic implants

So far, design and deployment of microelectronic, implantable devices has largely had a strongly ldquoad-hocrdquo character. The majority of existing devices has been custom-tailored to the specific application in mind, in an effort to abide by strict design constraints on safety as well as power and size. However, an enabling technology and the fact that implants are gradually becoming mainstream market products calls for a more structured design approach. Towards that end, in this paper we present ImpBench, a novel benchmark suite meant for designing and evaluating new digital processors for microelectronic implants. In an application field as wide as the various pathoses of the human body, we have conceptualized this suite based on common-sense and market-driven indicators, and we have established its usefulness and uniqueness based on extensive experimental measurement. The suite consists of eight carefully selected programs, chosen on the basis of popularity among contemporary and emerging implant applications. MiBench being the closest to our application field, that is embedded systems, has been used for a detailed comparative study. Since implants are required to perform control-, processing- or I/O-intensive tasks, various benchmark characteristics have been studied, namely: performance (IPC), cache and branch-prediction behavior, instruction distribution and power consumption. Results display significant variation from existing benchmarks to justify the need for and usefulness of ImpBench.

Profiling of symmetric-encryption algorithms for a novel biomedical-implant architecture

Starting with the implantable pacemaker, microelectronic implants have been around for more than 50 years. A plethora of commercial and research-oriented devices have been developed so far for a wide range of biomedical applications. In view of an envisioned expanding implant market in the years to come, our ongoing research work is focusing on the specification and design of a novel biomedical microprocessor core, carefully tailored to a large subset of existing and future biomedical applications. Towards this end, we have taken steps in identifying various tasks commonly required by such applications and profiling their behavior and requirements. One such task is decryption of incoming commands to an implant and encryption of outgoing (telemetered) biological data. Secure bidirectional information relaying in implants has been largely overlooked so far although protection of personal (biological) data is very crucial. In this context, we evaluate a large number of symmetric (block) ciphers in terms of various metrics: average and peak power consumption, total energy budget, encryption rate and efficiency, program-code size and security level. For our study we use XTREM, a performance and power simulator for Intels XScale embedded processor. Findings indicate the best-performing ciphers across most metrics to be MISTY1 (scores high in 5 out of 6 imposed metrics), IDEA and RC6 (both present in 4 out of 6 metrics). Further profiling of MISTY1 indicates a clear dominance of load/store, move and logic-operation instructions which gives us explicit directions for designing the architecture of our novel processor.

DeSyRe: On-demand system reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect-/fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints.

A system architecture, processor, and communication protocol for secure implants

Secure and energy-efficient communication between Implantable Medical Devices (IMDs) and authorized external users is attracting increasing attention these days. However, there currently exists no systematic approach to the problem, while solutions from neighboring fields, such as wireless sensor networks, are not directly transferable due to the peculiarities of the IMD domain. This work describes an original, efficient solution for secure IMD communication. A new implant system architecture is proposed, where security and main-implant functionality are made completely decoupled by running the tasks onto two separate cores. Wireless communication goes through a custom security ASIP, called SISC (Smart-Implant Security Core), which runs an energy-efficient security protocol. The security core is powered by RF-harvested energy until it performs external-reader authentication, providing an elegant defense mechanism against battery Denial-of-Service (DoS) and other, more common attacks. The system has been evaluated based on a realistic case study involving an artificial pancreas implant. When synthesized for a UMC 90nm CMOS ASIC technology, our system architecture achieves defense against unauthorized accesses having zero energy cost, running entity authentication through harvesting only 7.45μJ of RF energy from the requesting entity. In all other successfully authenticated accesses, our architecture achieves secure data exchange without affecting the performance of the main IMD functionality, adding less than 1‰ (1.3mJ) to the daily energy consumption of a typical implant. Compared to a singe-core, secure reference IMD, which would still be more vulnerable to some types of attacks, our secure system on chip (SoC) achieves high security levels at 56% energy savings and at an area overhead of less than 15%.

Profiling of lossless-compression algorithms for a novel biomedical-implant architecture

In view of a booming market for microelectronic implants, our ongoing research work is focusing on the specification and design of a novel biomedical microprocessor core targeting a large subset of existing and future biomedical applications. Towards this end, we have taken steps in identifying various tasks commonly required by such applications and profiling their behavior and requirements. A prominent family of such tasks is lossless data compression. In this work we profile a large collection of compression algorithms on suitably selected biomedical workloads. Compression ratio, average and peak power consumption, total energy budget, compression rate and program-code size metrics have been evaluated. Findings indicate the best-performing algorithms across most metrics to be mlzo (scores high in 5 out of 6 imposed metrics) and fin (present in 4 out of 6 metrics). Further mlzo profiling reveals the dominance of i) address-generation, load, branch and compare instructions, and ii) interdependent logical-logical and logical-compare instructions combinations.

Enhancing Heart-Beat-Based Security for mHealth Applications

In heart-beat-based security, a security key is derived from the time difference between consecutive heart beats (the inter-pulse interval, IPI), which may, subsequently, be used to enable secure communication. While heart-beat-based security holds promise in mobile health (mHealth) applications, there currently exists no work that provides a detailed characterization of the delivered security in a real system. In this paper, we evaluate the strength of IPI-based security keys in the context of entity authentication. We investigate several aspects that should be considered in practice, including subjects with reduced heart-rate variability (HRV), different sensor-sampling frequencies, intersensor variability (i.e., how accurate each entity may measure heart beats) as well as average and worst-case-authentication time. Contrary to the current state of the art, our evaluation demonstrates that authentication using multiple, less-entropic keys may actually increase the key strength by reducing the effects of intersensor variability. Moreover, we find that the maximal key strength of a 60-bit key varies between 29.2 bits and only 5.7 bits, depending on the subjects HRV. To improve security, we introduce the inter-multi-pulse interval (ImPI), a novel method of extracting entropy from the heart by considering the time difference between nonconsecutive heart beats. Given the same authentication time, using the ImPI for key generation increases key strength by up to 3.4

Accelerating complex brain-model simulations on GPU platforms

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