Chuen-Yau Chen

Novel low-power 1-bit full adder design

This paper propose a 1-bit low-power full adder that is designed by taking the advantage of the concept of pass-transistor logic and the concept of dual-threshold domino logic. The concept of pass-transistor logic is used to design the circuit generating the sum signal such that the number of transistors can be reduced. The concept of dual-threshold domino logic is adapted to design the circuit generating the carryout signal such that the operation can be speeded up. This full adder was designed with a TSMC 0.18-µm 1P6M CMOS process. The HSPICE simulation results show that this design achieves a superior performance with a power-delay product of 48.98 fJ for the SUM circuit and 16.19 fJ for the CARRYOUT circuit at 1.8-V supply voltage.

High-Resolution Architecture for CORDIC Algorithm Realization

This paper proposed a high-resolution architecture to implement the CORDIC algorithm. The addition identities of the trigonometric functions are adopted to determine the range of sine/cosine functions from the domain [0, 2pi] based on that restricted in the domain [0, pi/8]. The shrinking in domain of sine/cosine functions leads to about 50% reduction on the size of ROM lookup table and a 1-bit improvement on the precision in the CORDIC implementation

Combining concepts of inertia weights and constriction factors in particle swarm optimization

A particle swarm optimization algorithm with global star topology designed by combining the concepts of the inertia weight and constriction factor is proposed in this paper. We enhance the global search ability at the beginning, while slowing down in the local search when the particles are near the local minimum by the linearly decreasing inertia weight. We apply the constriction factor with a value of 0.729 scales down the velocity step sizes, such that the particles can move without large overshoots at the beginning and smoothly approach the goals with a series of small steps when the particles are near the area of the optimal solution prior to the end of iterations. For a a quick convergence, the global star topology is chosen in this algorithm. The simulations performed on 2 well-known benchmark functions for over 50 runs indicate that the proposed algorithm with a population size of only 20 particles can achieve the goals quickly and accurately.

Adaptive filter based on TDBLMS algorithm for image noise cancellation

An adaptive filter for two-dimensional block processing in image noise cancellation is proposed in this paper. The processing includes two phases. They are the weight-training phase and the block-adaptation phase. The weight-training phase obtains the suitable weight matrix to be the initial one for the block-adaptation phase such that a higher signal-to-noise ratio can be achieved. To verify the feasibility of this approach, the simulation with the block sizes of 4×4, 8×8, 16×16, and 32×32 are performed. The simulation results show that this approach performs well

Design of current-mode digital-to-analog converter in hybrid architecture

This paper proposed a current-mode digital-to-analog converter with a high resolution, high speed, and small hardware overhead. This design takes advantage of the weighted-current-steering approach and the R-/spl beta/R-ladder approach. The weighted-current-steering approach is used to implement the seven bits in the most-significant-bit stage while the R-/spl beta/R-ladder approach that is modified form the R-/spl beta/R approach is used to implement the nine bits in the least-significant-bit stage. This converter was designed with a TSMC 0.18-/spl mu/m 1P6M CMOS process. The HSPICE simulation results show that this design achieves a 16-b resolution with DNL and INL less than 0.5 LSB and 0.7 LSB, respectively. At 3.3-V supply voltage and 200-MHz operating frequency, the power consumption is 232 mW.

AMBA-based SDRAM controller intellectual property design

A digital intellectual property of SDRAM controller with a wrapper compatible with the AMBA is proposed in this paper. For the purpose of reusability, most of the control variables are parametrised to provide the high flexibility for controlling the SDRAMs with various specifications. The function of this design was simulated with ModelSim, Cadence, and Verilog-XL; the Verification Navigator was adopted to check the rules in Reuse Methodology Manual; logic synthesis was performed by Synopsys. The whole design was verified by controlling Micron 128-Mb SDRAM MT48LC4M32B2. The simulation results show that this design performs well.

Current-mode digital-to-analog converter designed in hybrid architecture

A current-mode digital-to-analog converter designed by combining the weighted-current-steering approach and the R-βR ladder approach is proposed in this paper. The weighted-current-steering approach is used to implement the seven bits in the most-significant-bit stage while the R-βR ladder approach that is modified form the R-2R approach is used to implement the nine bits in the least-significant-bit stage. This converter was designed with a TSMC 0.18 µm 1P6M CMOS process. Simulation results show that this design achieves a 16 b resolution with DNL and INL less than 0.5 LSB and 0.7 LSB, respectively. At 3.3 V supply voltage and 200 MHz operating frequency, the power consumption is 232 mW.

128-point memory-based architecture for a fast Fourier transform

In this article, we take advantage of the merits of a one-sixteenth circle storage technique, radix-2 and radix-2/4/8 algorithms to implement a 128-point memory-based architecture for a fast Fourier transform processor. The one-sixteenth circle storage technique results in reducing 50% of the size of a look-up table (LUT) for storing the twiddle factors. The combination of radix-2 and radix-2/4/8 algorithms results in reducing the number of twiddle factors and allowing the processor to possess a regular architecture which is suitable for hardware implementation. This design has been synthesised by Altera Quartus II 6.0. The experimental results indicate that this design needs only 65,169 ALUTs for LUT. The operating frequency is 59.76 MHz. The signal-to-noise ratios for the real and imaginary parts of the output signal are 67.72 dB and 68.55 dB, respectively.

TDBLMS-Based Adaptive Filter for Image SNR Enhancement

In this paper, we proposed an image noise canceller achieved by an adaptive filter in two-dimensional block processing based on the least-mean-square algorithm. In this adaptive filter, each image is processed in two phases. In the initial weight matrix decision phase, the block-by-block operations with the smaller block size of 4 × 4 are applied to the original noisy image for getting the suitable weight matrix that will be used as the initial one for the block-adaptation phase such that a higher signal-to-noise ratio can be achieved. To verify the feasibility of this approach, the simulations in the block-adaptation phase with the block sizes of 4 × 4, 8 × 8, 16 × 16, and 32 × 32 are performed. The simulation results show that this approach achieves a higher signal-to-noise ratio in each case of block size. Index Terms—Adaptive filter, noise cancellation, least- mean-square

High-efficiency test pattern generating mechanism

A high-efficiency test pattern generating mechanism blending the weighted-random-pattern generator and the controllable-linear-feedback-shift register is proposed in this paper. This mechanism tests a logic circuit in two phases. In the first phase, the weighted-random-pattern generator generates the test patterns to drop some of the faults from the fault list containing the faults that have not been tested in the initial testing performed by the patterns generated from the automatic-test-pattern generator. In the second phase, the controllable-linear-feedback-shift register generates the test patterns to test the deterministic faults that have not been tested in the first phase. We adopt controllable-linear- feedback-shift register to generate the deterministic patterns instead of modifying the configuration of the weighted-random-pattern generator such that a better fault coverage can be achieved with a lower hardware penalty and a shorter test length.