Chul-Ho Shin

Dynamic scheduling issues in SMT architectures

Simultaneous multithreading (SMT) attempts to attain higher processor utilization by allowing instructions from multiple independent threads to coexist in a processor and compete for shared resources. Previous studies have shown, however, that its throughput may be limited by the number of threads. A reason is that a fixed thread scheduling policy cannot be optimal for the varying mixes of threads it may face in an SMT processor. Our adaptive dynamic thread scheduling (ADTS) was previously proposed to achieve higher utilization by allowing a detector thread to make use of wasted pipeline slots with nominal hardware and software costs. The detector thread adaptively switches between various fetch policies. Our previous study showed that a single fixed thread scheduling policy presents much room (some 30%) for improvement compared to an oracle-scheduled case. In this paper, we take a closer look at ADTS. We implemented the functional model of the ADTS and its software architecture to evaluate various heuristics for determining a better fetch policy for a next scheduling quantum. We report that performance could be improved by as much as 25%.

Fast exploration of parameterized bus architecture for communication-centric SoC design

For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an SoC design. Furthermore, bus IP vendors provide software tools that automatically generate RTL codes of a bus once its designer configures it. Configurability, however, imposes more challenges upon designers because complexity involved in optimization increases exponentially as the number of parameters grows. In this paper, we present a novel approach with which effort requirement can be dramatically reduced. An automated optimization tool we developed is used and it exploits a genetic algorithm for fast design exploration. This paper shows that the time for the optimizing task can be reduced by more than 90% when the tool is used and, more significantly the task can be done without an experts hand while ending up with a better solution.

Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture

A transaction level modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented the transaction-level model of a proprietary bus called AHB+ which supports an extended AMBA2.0 protocol. The AHB+ transaction-level model is shown to be 353 times faster than the pin-accurate RTL model, while maintaining 97% accuracy on average. We also present the TLM development procedure of a bus architecture.

Patterning process for semiconductor using directed self assembly

Directed self-assembly (DSA) process of block copolymers (BCPs) has been considered as a candidate for sub-20nm contact patterning. In recent years the semiconductor manufacturers have been interested in use DSA in production. DSA is based on the intrinsic property of the BCPs which is phase-separation in the molecular scale, but significant problems remain for device application. Process time, high process temperature, defect, and CD distribution make the using of DSA difficult in mass production. One of the most considered problems for DSA is the CD Distribution. A guide material for grapho-epitaxy DSA process requires resistance against high temperature and solvent. We use negative tone develop (NTD) photoresist (PR) guide for simple process and thermal resistance, and additional treatment for resistance against high temperature and solvent. The CD distribution of DSA is highly related to the phase separation itself. In order to get better performance, the polymer chains should have sufficient mobility under heating above their glass temperature. Therefore, film thickness and molecular weight of BCPs are very important parameters for CD distribution of DSA process. From the results, it is proven that guide materials, film thickness of BCPs, and molecular weight of BCPs are significant parameter in order to improve CD distribution of DSA patterns.

THE NEED FOR ADAPTIVE DYNAMIC THREAD SCHEDULING IN SIMULTANEOUS MULTITHREADING

Earlier studies on Simultaneous Multithreaded (SMT) architectures showed that performance of a realistic SMT architecture saturates early. This paper addresses our contention that a fixed hardware thread scheduling strategy cannot provide optimal results for various thread combinations. We propose an approach that partially schedules threads in the form of a detector thread at a nominal hardware and software cost. It offers the capability to adaptively switch thread scheduling policies depending on various situations. This article shows that there is much room for performance improvement for our adaptive dynamic thread scheduling approach. The results we have obtained by simulating a realistic SMT architecture show that no single fetch policy may outperform the rest more than 50% of the total time. We show that 27% is approximately the upper-bound of the performance improvement for SMT with eight contexts. This demonstrates that our approach may significantly improve performance with good low-throughput detection and fetch policy selection heuristics.

The need for adaptive dynamic thread scheduling

Earlier studies on Simultaneous Multithreaded (SMT) Architectures showed that performance of a realistic SMT architecture saturates early. This paper addresses our contention that a fixed hardware thread scheduling strategy cannot provide optimal results for various thread combinations. We propose an approach that partially schedules threads in the form of a detector thread at a nominal hardware and software cost. It offers the capability to adaptively switch thread scheduling policies depending on various situations. This article shows that there is much room for performance improvement for our adaptive dynamic thread scheduling approach. The results obtained by simulating a realistic SMT architecture show that 27% is approximately the upper-bound of the performance improvement for SMT with eight contexts. This demonstrates that our approach may significantly improve performance with good low-throughput detection and fetch policy selection heuristics.