Chun-Shih Huang

A Novel SFVM-M

This paper presents an open-loop synchronized-OFF voltage-mode Master-made-modulated (SFVM-M 3) control scheme for a two-phase interleaved boost converter with Master-Slave strategy for power factor correction applications. Interleaving the continuous-conduction-mode and discontinuous-conduction-mode (CCM/DCM) boundary-mode boost converters, however, is complicated because of the variable-frequencies nature of the operation. Furthermore, a problem of current divergence is implied in the Slave converter. In this paper, an ON-time tuning scheme of Slave converter is presented to stabilize the interleaved converter without using a phase-lock loop, or multiplier and current sensors. It can be implemented not only by an analog circuit, but also an alternative approach, which is calculated by a digital processor such as DSP. In the following discussion, an analog circuit will be proposed to generate the M3 control signal and verify the stability of interleaved boost converter with SFVM-M 3 control scheme, and then a digital implementation will be proposed to design the SFVM-M3 controller.

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In this paper, an interleaved soft-switching dc-to-dc converter configuration is proposed. It consists of two parts: the primary side is a constant-frequency asymmetrical converter with active-clamp feature and the secondary side is a series-resonant tank circuit. The active-clamp circuit recycles the energy stored in the magnetizing inductance of transformer to allow main/auxiliary switches turn-ON at zero-voltage switching and clamps the voltage stress of the main switches. Series-resonant tank circuit employs the transformer leakage inductance and secondary resonant capacitance to achieve zero-current switching of the output diodes. The circuit features constant-frequency operation and soft switching for both the transistors and the diodes. Interleaving operation of this configuration combines the aforementioned benefits and small output capacitor. Theoretical analysis and computer simulation of the converter were given. An 80-KHz 500-W experimental circuit of the proposed converter was demonstrated.

Control Scheme for Interleaved CCM/DCM Boundary-Mode Boost Converter in PFC Applications

Peak current control (PCC) can be used to achieve adaptive voltage positioning (AVP) in DC power converters for CPU power applications. However, PCC is seldom used because of the problem with output voltage offset from the target load line. A novel high-gain PCC (HGPCC) AVP scheme was recently reported to correct the aforementioned offset problem while retaining the advantages of PCC, such as easy phase-current balancing, inherently cycle-to-cycle protection, and good stability margin. Without an analytical model, however, it is very hard to achieve prescribed characteristics using this complicated scheme. In this paper, a control model and design considerations will be presented for this scheme. Key equations for converter feedback performance and rules for compensating the feedback loop will be presented. The proposed model was experimentally verified.

Interleaved Active-Clamping Converter With ZVS/ZCS Features

A single-inductor dual-output (SIDO) buck converter has recently found applications in hand-held battery-powered electronic devices. The circuit operation and the functional interdependencies among basic converter parameters such as DC voltage gains, transistor duty cycles, and load current levels are much more complicated than those of the single-output counterpart. In this paper, a rigorous analysis was conducted to develop DC equations for the converters. More importantly, from the analysis results, a possibility of a new mode of operation, dubbed “mix-buck” operation, will be pointed out. In the so-called “mix-buck” operation, the converter is capable of working even when the input voltage is lower than one of the two output voltages. In the past, a SIDO buck converter has been used for providing “pure-buck” outputs, i.e., both output voltages are lower than the input voltage. Therefore, this possibility not only opens up new applications but also may extend the operating battery range in existing applications. Experimental results confirmed the DC equations and the “mix-buck” operation of SIDO converters.

Modeling and Design Considerations of a Novel High-Gain Peak Current Control Scheme to Achieve Adaptive Voltage Positioning (AVP) for DC Power Converters

In recent years, single-inductor dual-output (SIDO) converters have found applications in hand-held electronic devices. The focus of the paper is about the modeling and the design of the feedback control loop for a voltage-mode SIDO buck converter working in continuous conduction mode. A small-signal model was developed and verified by simulations and experimental results. This model is practically useful in designing the feedback compensation and predicting the closed-loop performances including circuit stability, line regulation, and output impedances.

Mix-Voltage Conversion for Single-Inductor Dual-Output Buck Converters

A critical-mode (CRM) operation has recently been used for low-to-medium power-level power factor correction (PFC) boost converter circuit. In theory, this circuit provides very good power factor and little distortion. However, in a real circuit, the input current of such operation suffers from significant input current distortion. In this paper, the phenomenon of input current distortion was analyzed, and the cause was traced to the parasitic capacitance of the MOSFET switch. An on-time adjustment control scheme, based on rigorous mathematical analysis, was proposed to overcome this problem. In addition, zero voltage switching (ZVS) operation was incorporated into this new scheme. An implementation of the proposed strategy was also presented. Simulations were conducted to verify the validity of the proposed scheme.

Modeling and design of feedback loops for a voltage-mode single-inductor dual-output buck converter

In this paper, an interleaved soft-switching dc-to-dc converter configuration is proposed. It consists of two parts: the primary side is a constant-frequency asymmetrical converter with active-clamp feature and the secondary side is a series-resonant tank circuit. The active-clamp circuit recycles the energy stored in the magnetizing inductance of transformer to allow main/auxiliary switches turn-ON at zero-voltage switching and clamps the voltage stress of the main switches. Series-resonant tank circuit employs the transformer leakage inductance and secondary resonant capacitance to achieve zero-current switching of the output diodes. The circuit features constant-frequency operation and soft switching for both the transistors and the diodes. Interleaving operation of this configuration combines the aforementioned benefits and small output capacitor. Theoretical analysis and computer simulation of the converter were given. An 80-KHz 500-W experimental circuit of the proposed converter was demonstrated.

A new on-time adjustment scheme for the reduction of input current distortion of critical-mode power factor correction boost converters

One-transistor (1T) memory cells with long data retention time is achieved with the modulation of drain current by channel traps. For simple demonstration, poly-Si TFTs are used, and grain boundary traps induced by excimer laser annealing are used as channel traps. The channel length in this work is 6 μm and the extrapolated data retention time can be as long as ~107 s at half of the current window. With the assumption that total number of traps is proportional to device volume and leakage current is proportional to the peripheral areas, retention time is scaled with gate length. For 30 nm devices, retention time is estimated to be ≥ 5×104 s. Compared with the conventional Zero-capacitor random access memory (Z-RAM), the channel trap memory provides better retention characteristics. For practical applications, the new channel trap cell has the same gate structure as logic devices, and can be potentially embedded in SoC platform. Due to the defect tolerance of cell channel and the low-temperature process, the 3D (multi-layer) memory structure by stacking the cells vertically can be potentially implemented more easily than flashtype devices [1]. In principle, the channel traps cells can also be implemented in bulk Si and the localized channel traps can be formed in the scaled devices using implantation techniques. This paper proposes a design of 1T memory cells that utilizes the modulation of drain current by channel traps and offers these advantages: 1. capacitorless structure, 2. long data retention time, 3. excellent endurance characteristics, 4. low power consumption, 5. 3D integration compatibility.

Interleaved active-clamping converter with ZVS/ZCS features

A single-inductor dual-output (SIDO) buck converter has recently found applications in hand-held battery-powered electronic devices. The circuit operation and the functional interdependencies among basic converter parameters such as dc voltage gains, transistor duty cycles, and load current levels are much more complicated than those of the single-output counterpart. In this paper, a rigorous analysis was conducted to develop dc equations in steady-state operation for SIDO converters. More importantly, from the analysis results, a possibility of a new mode of operation, dubbed “mix-voltage” operation, will be pointed out. In the so-called “mix-voltage” operation, the converter is capable of working even when the input voltage is lower than one of the two output voltages. In the past, a SIDO buck converter has been used for providing “pure-buck” outputs, i.e., both output voltages are lower than the input voltage. Therefore, this possibility not only opens up new applications but also extends the operating battery range in existing applications. Experimental results confirmed the dc equations and the “mix-voltage” conversion of SIDO buck converters.

A design of 1T memory cells using channel traps for long data retention time

In this paper a-Si:H TFTs with the external the mechanical strain and bending cycles is studied. In addition, the trap states distribution is also discussed. Besides, the temperature distribution of a-Si:H TFTs on plastic substrate is an important issue for operation. A thermal conduction layer dissipates the accumulated heat during operation is designed and it calculates the temperature distribution in this work.