Chung-Heon Lee

A 130nm 1.1V 143MHz SRAM-like embedded DRAM COMPILER with Dual Asymmetric bit line Sensing Scheme and quiet unselected IO scheme

A SRAM-like embedded DRAM compiler with 0.13um technology was designed using two novel circuit schemes. Firstly, Dual Asymmetric bit line Sensing Scheme is proposed to implement VDD bit line pre-charge scheme without any reference cells and half charge generator. Therefore, we overcame the risk of failure caused by defects in reference cells and simplified embodying VDD bit line pre-charge scheme, enjoying privileges of VDD bit line pre-charge scheme such as fast sensing speed (tRC:7ns, tAC:6.7ns in this work) and stable sensing operation at low voltage and low temperature. Secondly, we propose circuit idea for quiet unselected IO lines. Unselected IO lines are not developed by bit line data during READ/WRITE operation. This scheme has advantage in the architecture with wide IO and various IO multiplexing options like a memory compiler.

Investigation on spin-on hard mask integration

For fine patterning, there are two possible hard mask integration schemes: quad-layer and tri-layer systems. Due to the different structures and processes between quad- and tri- layer systems, each system needs specific chemical and physical properties of the hard mask. In this paper, we report the properties of the carbon-based spin-on hard mask (CSOH) candidates for various hard mask integrations.