Chung-Lin Wu

Multi-flip chip on lead frame overmolded IC package: a novel packaging design to achieve high performance and cost effective module package

Miniaturization reduces package size, cost and board space. System on Chip (SoC) integrates a system on a common silicon substrate, however there are some shortcomings with this approach such as high manufacturing cost. Handling of different levels of voltage and current on a common silicon substrate with controller IC operating in the range of several volts and milliamps, while power MosFETs at over hundreds of volts and more dozens of amps can also pose as an issue. Nevertheless, module packages having controller IC and power MosFET co-packaged are new. Fairchild semiconductors advancement in packaging has eliminated these drawbacks with the introduction of multi-flip chip on lead frame over-molded IC package. This new package has a novel packaging concept that uses multi-flip chip technology on the power devices combined with controller IC employing wire bonding technique on one copper lead frame based substrate. The gate and source in power MosFETs are bumped and attached to the copper lead frame by flip chip bonding technology and are routed out of package by solder balls while the drain exposed at the bottom of the package is soldered directly to the board. This is a BGA package with exposed die back for drain. The paper describes the construction of multi-flip chip on lead frame over molded package in Fairchild Semiconductor, its cost effective package designs and manufacturing challenges.

Modeling for defects impact on electrical performance of power packages

The electrical performance (such as electrical resistance, inductance and fusing current capability) is a key factor for a power electronic product. Studying the impact of the defect on package electrical performance, especially for the parasitic effect is very important. It can help to understand the potential root causes and failure mechanisms, as well as to ensure the electrical performance meets the product requirements by optimizing the package design and assembly process. The objective of this paper is to study the impact of wire bonding-related defects and the die attach solder voids for the electrical resistance, inductance and fusing current capability of the power packages. The major work in this paper consists of two parts. One is the impact of wire bonding-related defects on the electrical performance of the power package. The other is the impact of die attach (DA) solder void. Both electrical and coupled thermal electrical simulations are conducted to study the wire bonding-related defects and DA solder voids of different levels. Simulation results show that the resistance and inductance of the package are not sensitive to the wire bond defects. However, the wire bond defects may induce significant impact on the fusing current capability of the package. For die attach voids, the inductance of the package seems not sensitive to the die attach voids while the electrical resistance has been affected significantly.

Optocoupler BGA package

The article presents the design of an optocoupler BGA. A low profile miniature surface mount component is described up to 1.20 mm in height having a footprint smaller than the current PDIP form factors. The optocoupler BGA does not need encapsulation (mold compounds) and its manufacturing tooling is form factor independent. Its design also lends itself to improved reliability performance in accelerated tests such as thermal cycling. Using Pb-free solder balls an all Pb-free package can be constructed.