Chunhao Wang

Computational study on bidimensionality theory based algorithm for longest path problem

Bidimensionality theory provides a general framework for developing subexponential fixed parameter algorithms for NP-hard problems. In this framework, to solve an optimization problem in a graph G, the branchwidth

Global register alias table: Boosting sequential program on multi-core

{\mathop{\rm bw}}(G)

Global Register Alias Table: Executing Sequential Program on Multi-Core

is first computed or estimated. If

Implementing method of multi-core system structure with buffer window

{\mathop{\rm bw}}(G)

Near-linear constructions of exact unitary 2-designs.

is small then the problem is solved by a branch-decomposition based algorithm which typically runs in polynomial time in the size of G but in exponential time in

Network-on-chip router having adaptive routing capability and implementing method thereof

{\mathop{\rm bw}}(G)

Implementation method of rename table of global register under on-chip multi-processor system framework

. Otherwise, a large

Control method of general-purpose operating system for accessing CPU two stage caching

{\mathop{\rm bw}}(G)

Software transaction internal memory implementing method based on delaying policy

implies a large grid minor of G and the problem is computed or estimated based on the grid minor. A representative example of such algorithms is the one for the longest path problem in planar graphs. Although many subexponential fixed parameter algorithms have been developed based on bidimensionality theory, little is known on the practical performance of these algorithms. We report a computational study on the practical performance of a bidimensionality theory based algorithm for the longest path problem in planar graphs. The results show that the algorithm is practical for computing/estimating the longest path in a planar graph. The tools developed and data obtained in this study may be useful in other bidimensional algorithm studies.

Implementing method for network-on-chip data packet encoding optimization

Executing sequential program on multi-core is crucial for accommodating Instruction Level Parallelism (ILP) in Chip Multi-Processor (CMP) architecture. One widely used method for steering instructions across cores is based on dependency. However, this method requires a sophisticated steering mechanism and brings about much hardware complexity and die area overhead. This paper presents the Global Register Alias Table (GRAT), a structure which can be used in CMP architecture to facilitate sequential program execution across cores. The GRAT drastically reduces the area overhead and design complexity of steering instructions without introducing additional programming effort or compiler support. Dynamic reconfiguration is also implemented to support efficient parallel program execution. In our evaluation, the result shows that our work performs within 5.9% of Core Fusion, a recent work which requires a complex steering unit.