Chunhong Chen

Activity-driven clock design

In this paper, we investigate reducing the power consumption of a synchronous digital system by minimizing the total power consumed by the clock signals. We construct activity-driven clock trees wherein sections of the clock tree are turned off by gating the clock signals. Since gating the clock signal implies that additional control signals and gates are needed, there exists a tradeoff between the amount of clock tree gating and the total power consumption of the clock tree. We exploit similarities in the switching activity of the clocked modules to reduce the number of clock gates. Assuming a given switching activity of the modules, we propose three novel activity-driven problems: a clock tree construction problem, a clock gate insertion problem, and a zero-skew clock gate insertion problem. The objective of these problems is to minimize the systems power consumption by constructing an activity-driven clock tree. We propose an approximation algorithm based on recursive matching to solve the clock tree construction problem. We also propose an exact algorithm employing the dynamic programming paradigm to solve the gate insertion problems. Finally, we present experimental results that verify the effectiveness of our approach. This paper is a step in understanding how high-level decisions (e.g., behavioral design) can affect a low-level design (e.g., clock design).

Activity-sensitive clock tree construction for low power

This paper presents an activity-sensitive clock tree construction technique for low power design of VLSI clock networks. We introduce the term of node difference based on module activity information, and show its relationship with the power consumption. A binary clock tree is built using the node difference between different modules to optimize the power consumption due to the interconnections (i.e., clock gating signals and clock edges). We also develop a method to determine gating signals with minimum number of transitions. After the clock tree is constructed, the gating signals are optimized for further power savings.

Simultaneous voltage scaling and gate sizing for low-power design

This paper presents a new approach using simultaneous voltage-scaling and gate-sizing for low power without violating the timing constraints. We provide the problem formulation in this application, and propose algorithms for single voltage-scaling, single gate-sizing, and their simultaneous manipulation. We target a globally optimal solution by showing how the power optimization is related to the maximum-weighted-independent-set (MWIS) problem. Experimental results on a set of benchmark circuits show that the simultaneous voltage-scaling and gate-sizing generates maximum power reduction. The average power savings range from 23% to 57% over all tested circuits, depending upon the circuit topology, underlying gate library and specific supply voltages.

Power efficient multi-stage CMOS rectifier design for UHF RFID tags

Power efficiency of a UHF rectifier circuit, which is part of long-range IC-based passive RFID tags, has become a serious bottleneck in implementing power-hungry intelligent sensors. This paper presents an analytical approach for multi-stage rectifiers, which provides design tradeoffs as well as a set of design rules to improve power efficiency of the rectifier. As an example, three-stage rectifiers are designed with ST 90nm CMOS technology for optimized performance at both 10 and 22m distances. When compared with existing results at the same level of output power, the proposed rectifiers show a 3x better performance in power efficiency (73%) and 55% reduction in power-up threshold with longer operating range.

Timing driven gate duplication

In the past few years, gate duplication has been studied as a strategy for cutset minimization in partitioning problems. This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary inputs(PI) in topologically sorted order evaluating tuples at the input pins of gates. The tuples first component corresponds to the input pin required time if that gate is not duplicated. The second component corresponds to the input pin required time if that gate were duplicated. After tuple evaluation the algorithm traverses the network from PI to PO in topologically sorted order, deciding the gates to be duplicated. The last and final traversal is again from PO to PI, in which the gates are physically duplicated. Our algorithm uses the dynamic programming structure. We report delay improvements over other optimization methodologies. Gate duplication, along with other optimization strategies, can be used for meeting the stringent delay constraints in todays ultra complex designs.

Binary Multiplication Using Hybrid MOS and Multi-Gate Single-Electron Transistors

In this paper, we investigate the design of binary tree multipliers based on multi-input counters using hybrid MOS and single-electron transistors (SETs). Our focus is on the design of phase-modulated counters which can be implemented with only a few MOSFETs and multi-gate SETs. In order to address some practical issues associated with SET/MOS hybrid circuits, we present an enhanced version of the counters to deal with temperature effect, reliability improvement, and operating speed with multipliers. Simulation results with the proposed phase-modulated (7:3) counter show that it is able to work at room temperature with a delay of 1.5 ns, power dissipation of 4.1 μW at frequency of 100 MHz, and maximum tolerable background charges of up to 0.2e with the worst-case delay of 3 ns.

Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis

Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a given control-dominated data flow graph. We discuss delay and power issues with scheduling, and propose an improvement algorithm for insertion of so-called soft edges which enable power optimization under timing constraints. Power savings obtained by our approach on tested circuits range between 15 % and 30 % of the initial power dissipation.

An ultra-low power ring oscillator for passive UHF RFID transponders

This paper presents a new two-stage CMOS voltage-controlled ring oscillator (VCO) designed for passive UHF RFID transponders. The goal is to explore the design space for the lowest possible power dissipation. A nano-power VCO capable of functioning as a local oscillator for the transponders is obtained by biasing the delay cells to operate in weak inversion region. Further power reduction is achieved by transistor sizing. Designed in a 90nm CMOS technology, the proposed circuit generates oscillation signals at 5.12 MHz and consumes only 24nW with 0.3V power supply.

Reliability-Driven Gate Replication for Nanometer-Scale Digital Logic

To make digital circuits with unreliable devices more reliable has been a design challenge, especially for todays nanometer-scale technologies. In this paper, we discuss gate replication architecture towards increasing the reliability of individual logic gates. While this architecture is similar to, and a special case of, conventional N-modular redundancy scheme, we provide more interpretation and extend it to the situation where N is an even integer by using threshold logic gate instead of majority voter. We also study the reliability models for generic gates with single-electron tunneling (SET) technology. Both analysis and numerical evaluation suggest that while more redundancy leads to higher reliability in general, the improvement rate depends on individual gate failure rates

Delay Estimation on Single-Electron Tunneling-Based Logic Gates

The switching speed of single-electron tunneling (SET) logic devices is determined by their delay which, with the stochastic nature of electron transports, is still not well understood and characterized so far. This study looks at unique SET phenomena in SET logic gates and, for the first time, presents several approaches to estimate their delay, including an exact method and two approximate methods (namely, step estimation and fast estimation). Both theoretical analysis and application are shown to support the effectiveness of the proposed method, which also allow us to further explore the impacts of device parameters on the dynamic behavior of SET logic circuits.