Chunshan Du

An efficient lithographic hotspot severity analysis methodology using Calibre PATTERN MATCHING and DRC application

As the IC industry moves forward to advanced nodes, especially under 28nm technology, the printability issue is becoming more and more challenging because layouts are more congested with a smaller critical feature size and the manufacturing process window is tighter. Consequently, design-process co-optimization plays an important role in achieving a higher yield in a shorter tape-out time. A great effort has to be made to analyze the process defects and build checking kits to deliver the manufacturing information, by utilizing EDA software, to designers to dig out the potential manufacturing issues and quickly identify hotspots and prioritize how to fix them according to the severity levels. This paper presents a unique hotspot pattern analysis flow that SMIC has built for advanced technology to analyze the potential yield detractor patterns in millions of patterns from real designs and rank them with severity levels related to real fab process. The flow uses Mentor Graphics Calibre® PM (Calibre® Pattern Matching) technology for pattern library creation and pattern clustering; meanwhile it incorporates Calibre® LFD (Calibre® Litho-Friendly Design) technology for accurate simulation-based lithographic hotspot checking. Pattern building, clustering, scoring, ranking and fixing are introduced in detail in this paper.

Leveraging pattern matching to solve SRAM verification challenges at advanced nodes

Memory is a critical component in todays system-on-chip (SoC) designs. Static random-access memory (SRAM) blocks are assembled by combining intellectual property (IP) blocks that come from SRAM libraries developed and certified by the foundries for both functionality and a specific process node. Customers place these SRAM IP in their designs, adjusting as necessary to achieve DRC-clean results. However, any changes a customer makes to these SRAM IP during implementation, whether intentionally or in error, can impact yield and functionality. Physical verification of SRAM has always been a challenge, because these blocks usually contain smaller feature sizes and spacing constraints compared to traditional logic or other layout structures. At advanced nodes, critical dimension becomes smaller and smaller, until there is almost no opportunity to use optical proximity correction (OPC) and lithography to adjust the manufacturing process to mitigate the effects of any changes. The smaller process geometries, reduced supply voltages, increasing process variation, and manufacturing uncertainty mean accurate SRAM physical verification results are not only reaching new levels of difficulty, but also new levels of criticality for design success. In this paper, we explore the use of pattern matching to create an SRAM verification flow that provides both accurate, comprehensive coverage of the required checks and visual output to enable faster, more accurate error debugging. Our results indicate that pattern matching can enable foundries to improve SRAM manufacturing yield, while allowing designers to benefit from SRAM verification kits that can shorten the time to market.

A weak pattern random creation and scoring method for lithography process tuning

As the IC technology node moves forward, critical dimension becomes smaller and smaller, which brings huge challenge to IC manufacturing. Lithography is one of the most important steps during the whole manufacturing process and litho hotspots become a big source of yield detractors. Thus tuning lithographic recipes to cover a big range of litho hotspots is very essential to yield enhancing. During early technology developing stage, foundries only have limited customer layout data for recipe tuning. So collecting enough patterns is significant for process optimization. After accumulating enough patterns, a general way to treat them is not precise and applicable. Instead, an approach to scoring these patterns could provide a priority and reference to address different patterns more effectively. For example, the weakest group of patterns could be applied the most limited specs to ensure process robustness. This paper presents a new method of creation of real design alike patterns of multiple layers based on design rules using Layout Schema Generator (LSG) utility and a pattern scoring flow using Litho-friendly Design (LFD) and Pattern Matching. Through LSG, plenty of new unknown patterns could be created for further exploration. Then, litho simulation through LFD and topological matches by using Pattern Matching is applied on the output patterns of LSG. Finally, lithographical severity, printability properties and topological distribution of every pattern are collected. After a statistical analysis of pattern data, every pattern is given a relative score representing the pattern’s yield detracting level. By sorting the output pattern score tables, weak patterns could be filtered out for further research and process tuning. This pattern generation and scoring flow is demonstrated on 28nm logic technology node. A weak pattern library is created and scored to help improve recipe coverage of litho hotspots and enhance the reliability of process.

An efficient way of layout processing based on calibre DRC and pattern matching for defects inspection application

As technology advances, escalating layout design complexity and chip size make defect inspection becomes more challenging than ever before. The YE (Yield Enhancement) engineers are seeking for an efficient strategy to ensure accuracy without suffering running time. A smart way is to set different resolutions for different pattern structures, for examples, logic pattern areas have a higher scan resolution while the dummy areas have a lower resolution, SRAM area may have another different resolution. This can significantly reduce the scan processing time meanwhile the accuracy does not suffer. Due to the limitation of the inspection equipment, the layout must be processed in order to output the Care Area marker in line with the requirement of the equipment, for instance, the marker shapes must be rectangle and the number of the rectangle shapes should be as small as possible. The challenge is how to select the different Care Areas by pattern structures, merge the areas efficiently and then partition them into pieces of rectangle shapes. This paper presents a solution based on Calibre DRC and Pattern Matching. Calibre equation-based DRC is a powerful layout processing engine and Calibre Pattern Matching’s automated visual capture capability enables designers to define these geometries as layout patterns and store them in libraries which can be re-used in multiple design layouts. Pattern Matching simplifies the description of very complex relationships between pattern shapes efficiently and accurately. Pattern matching’s true power is on display when it is integrated with normal DRC deck. In this application of defects inspection, we first run Calibre DRC to get rule based Care Area then use Calibre Pattern Matching’s automated pattern capture capability to capture Care Area shapes which need a higher scan resolution with a tune able pattern halo. In the pattern matching step, when the patterns are matched, a bounding box marker will be output to identify the high resolution area. The equation-based DRC and Pattern Matching effectively work together for different scan phases.

A smart way to identify and extract repeated patterns of a layout

As integrated circuits (IC) technology moves forward, manufacturing process is facing more and more challenges. Optical proximity correction (OPC) has been playing an important role in the whole manufacturing process. In the deep sub-micron technology, OPC engineers not only need to guarantee the layout designs to be manufacturable but also take a more precise control of the critical patterns to ensure a high performance circuit. One of the tasks that would like to be performed is the consistency checking as the identical patterns under identical context should have identical OPC results in theory, like SRAM regions. Consistency checking is essentially a technique of repeated patterns identification, extraction and derived patterns (i.e. OPC results) comparison. The layout passing to the OPC team may not have enough design hierarchical information either because the original designs may have undergone several layout processing steps or some other unknown reasons. This paper presents a generic way to identify and extract repeated layout structures in SRAM regions purely based on layout pattern analysis through Calibre Pattern Matching and Calibre equation-based DRC (eqDRC). Without Pattern Matching and eqDRC, it will take lots of effort to manually get it done by trial and error, it is almost impossible to automate the pattern analysis process. Combining Pattern Matching and eqDRC opens a new way to implement this flow. The repeated patterns must have some fundamental features for measurement of pitches in the horizontal and vertical direction separately by Calibre eqDRC and meanwhile can be a helper to generate some anchor points which will be the starting points for Pattern Matching to capture patterns. The informative statistical report from the pattern search tells the match counts individually for each patterns captured. Experiment shows that this is a smart way of identifying and extracting repeated structures effectively. The OPC results are the derived layers on these repeated structures, by running pattern search using design layers as pattern layers and OPC results as marker layers, it is an easy job to compare the consistency.

Using pattern based layout comparison for a quick analysis of design changes

A design usually goes through several versions until achieving a most successful one. These changes between versions are not a complete substitution but a continual improvement, either fixing the known issues of its prior versions (engineering change order) or a more optimized design substitution of a portion of the design. On the manufacturing side, process engineers care more about the design pattern changes because any new pattern occurrence may be a killer of the yield. An effective and efficient way to narrow down the diagnosis scope appeals to the engineers. What is the best approach of comparing two layouts? A direct overlay of two layouts may not always work as even though most of the design instances will be kept in the layout from version to version, the actual placements may be different. An alternative way, pattern based layout comparison, comes to play. By expanding this application, it makes it possible to transfer the learning in one cycle to another and accelerate the process of failure analysis. This paper presents a solution to compare two layouts by using Calibre DRC and Pattern Matching. The key step in this flow is layout decomposition. In theory, with a fixed pattern size, a layout can always be decomposed into limited number of patterns by moving the pattern center around the layout, the number is limited but may be huge if the layout is not processed smartly! A mathematical answer is not what we are looking for but an engineering solution is more desired. Layouts must be decomposed into patterns with physical meaning in a smart way. When a layout is decomposed and patterns are classified, a pattern library with unique patterns inside is created for that layout. After individual pattern libraries for each layout are created, run pattern comparison utility provided by Calibre Pattern Matching to compare the pattern libraries, unique patterns will come out for each layout. This paper illustrates this flow in details and demonstrates the advantage of combining Calibre DRC and Calibre Pattern Matching.

Hotspots fixing flow in NTD process by using DTCO methodology at 10nm metal 1 layer

This paper proposes a novel hotspots fixing flow, in which design rule optimization and lithography RET solution are obtained simultaneously. This flow is most effective in the early development phase, and its methodology is rooted from design technology co-optimization (DTCO). Two layout files, corresponding to separate colors of a double-pattern layer (10nm node M1), are first generated by a pattern generator, and they meet no-stitching requirements and are design rule check (DRC) clean. Then, source, mask and design rule co-optimization is done with the layouts, and the design rules are optimized to remove hotspots and enable maximum lithography process window (PW). The mask optimization (MO) in combination with cost function manipulation and design rule optimization improve the robustness of initial design rule. The application of the methodology illustrates a friendly design rule and avoids later design rework.

A fast and efficient method for device level layout analysis

There is an increasing demand for device level layout analysis, especially as technology advances. The analysis is to study standard cells by extracting and classifying critical dimension parameters. There are couples of parameters to extract, like channel width, length, gate to active distance, and active to adjacent active distance, etc. for 14nm technology, there are some other parameters that are cared about. On the one hand, these parameters are very important for studying standard cell structures and spice model development with the goal of improving standard cell manufacturing yield and optimizing circuit performance; on the other hand, a full chip device statistics analysis can provide useful information to diagnose the yield issue. Device analysis is essential for standard cell customization and enhancements and manufacturability failure diagnosis. Traditional parasitic parameters extraction tool like Calibre xRC is powerful but it is not sufficient for this device level layout analysis application as engineers would like to review, classify and filter out the data more easily. This paper presents a fast and efficient method based on Calibre equation-based DRC (eqDRC). Equation-based DRC extends the traditional DRC technology to provide a flexible programmable modeling engine which allows the end user to define grouped multi-dimensional feature measurements using flexible mathematical expressions. This paper demonstrates how such an engine and its programming language can be used to implement critical device parameter extraction. The device parameters are extracted and stored in a DFM database which can be processed by Calibre YieldServer. YieldServer is data processing software that lets engineers query, manipulate, modify, and create data in a DFM database. These parameters, known as properties in eqDRC language, can be annotated back to the layout for easily review. Calibre DesignRev can create a HTML formatted report of the results displayed in Calibre RVE which makes it easy to share results among groups. This method has been proven and used in SMIC PDE team and SPICE team.

A random generation approach to pattern library creation for full chip lithographic simulation

As technology advances, the need for running lithographic (litho) checking for early detection of hotspots before tapeout has become essential. This process is important at all levels—from designing standard cells and small blocks to large intellectual property (IP) and full chip layouts. Litho simulation provides high accuracy for detecting printability issues due to problematic geometries, but it has the disadvantage of slow performance on large designs and blocks [1]. Foundries have found a good compromise solution for running litho simulation on full chips by filtering out potential candidate hotspot patterns using pattern matching (PM), and then performing simulation on the matched locations. The challenge has always been how to easily create a PM library of candidate patterns that provides both comprehensive coverage for litho problems and fast runtime performance. This paper presents a new strategy for generating candidate real design patterns through a random generation approach using a layout schema generator (LSG) utility. The output patterns from the LSG are simulated, and then classified by a scoring mechanism that categorizes patterns according to the severity of the hotspots, probability of their presence in the design, and the likelihood of the pattern causing a hotspot. The scoring output helps to filter out the yield problematic patterns that should be removed from any standard cell design, and also to define potential problematic patterns that must be simulated within a bigger context to decide whether or not they represent an actual hotspot. This flow is demonstrated on SMIC 14nm technology, creating a candidate hotspot pattern library that can be used in full chip simulation with very high coverage and robust performance.

Litho hotspots fixing using model based algorithm

As technology advances, IC designs are getting more sophisticated, thus it becomes more critical and challenging to fix printability issues in the design flow. Running lithography checks before tapeout is now mandatory for designers, which creates a need for more advanced and easy-to-use techniques for fixing hotspots found after lithographic simulation without creating a new design rule checking (DRC) violation or generating a new hotspot. This paper presents a new methodology for fixing hotspots on layouts while using the same engine currently used to detect the hotspots. The fix is achieved by applying minimum movement of edges causing the hotspot, with consideration of DRC constraints. The fix is internally simulated by the lithographic simulation engine to verify that the hotspot is eliminated and that no new hotspot is generated by the new edge locations. Hotspot fix checking is enhanced by adding DRC checks to the litho-friendly design (LFD) rule file to guarantee that any fix options that violate DRC checks are removed from the output hint file. This extra checking eliminates the need to re-run both DRC and LFD checks to ensure the change successfully fixed the hotspot, which saves time and simplifies the designer’s workflow. This methodology is demonstrated on industrial designs, where the fixing rate of single and dual layer hotspots is reported.