Cindy Norris

An experimental study of several cooperative register allocation and instruction scheduling strategies

Compile-time reordering of low level instructions is successful in achieving large increases in performance of programs on fine-grain parallel machines. However, because of the interdependences between instruction scheduling rand register allocation, a lack of cooperation between the schedules and register allocator can result in generating code that contains excess register spills and/or a lower degree of parallelism than actually achievable. This paper describes a strategy for providing cooperation between register allocation and both global and local instruction scheduling. We experimentally compare this strategy with other cooperative and uncooperative scenarios. Our experiments indicate that the greatest speedups are obtained by performing either cooperative or uncooperative global instruction scheduling with cooperative register allocation and local instruction scheduling.

The design and implementation of RAP: a PDG-based register allocator

This paper describes the design and implementation of a register allocator that performs the allocation over the Program Dependence Graph (PDG) representation of a routine. The PDG representation has been used successfully as the basis for various scalar optimizations, as well as for detecting and improving parallelization for vector machines, multiple processor machines, and architectures that exhibit instruction level parallelism. Variations of the PDG have also been used for debugging and integrating different versions of a program via program‐slicing, and to enable translation of imperative programs for data‐flow machines and demand‐driven graph reducers. By basing register allocation on the PDG, the register allocation phase may be more easily integrated and intertwined with other optimization analyses and transformations. In addition, the advantages of a hierarchical approach to global register allocation can be attained without constructing an additional structure used solely for register allocation.

Computing curricula 2001 draft

cussion of the CC2001 drafts treatment of programming languages was conducted on the SIGCSE (Computer Science Education) mailing list. The SIGPLAN Executive Committee shared these concerns with the Curricula draft, and have responded with a letter to the CC 2001 Task Force which is included below. During the SIGCSE symposium in February, a session was held for presentation and discussion of the CC 2001 draft. It was stated during that session that the number of core hours for programming languages would likely be increased from 6 to 19. The CC 2001 Task Force is inviting the public to make comments about the ironman draft. We encourage you to examine the draft and give feedback to the CC 200t Task Force. The draft and a forum for providing comments can be accessed from

Profile assisted register allocation

Register allocation is a phase of the compiler in which physical registers are assigned variables to reduce accesses into memory. When there are not enough physical registers for all the variables, then one or more of the variables must be spilled to memory. Spilling consists of storing the variable to memory after the variable has been defined, and loading the variable from memory before using it. Current register allocation techniques, no matter how efficient, will have to insert spill code into the program due to the lack of registers. To decide the best candidate for spilling, the register allocator computes the spill cost for each variable. These spill costs are based on estimates of the overhead that would be added to the program by spilling the variable. This research investigates using profiling information to formulate the spill costs used by the register allocation phase. Profiling is a technique which collects information about the run-time behavior of a program. Our profile assisted register allocator uses the profiling information to calculate accurate spill costs. The experimental study indicates that profile assisted allocation can result in code which executes faster than code allocated using standard spill cost estimates.

Scientific experimentation via the matching game

In traditional computer science curricula, students view program implementation as the end product and not the means to obtaining some further result. All too often students complete an implementation at the last minute, perform a minimal amount of testing and call the assignment done! This paper discusses an approach we have taken in our courses to have students use and develop programs as part of a scientific inquiry. In addition to causing students to perform more thorough testing, our approach also improves empirical and critical thinking skills.

Evaluating the use of profiling by a region-based register allocator

In a region-based compilation framework, the compiler builds regions to provide the best compilation unit for scheduling and optimization. The compiler uses execution frequency information gained from profiling to place frequently executed blocks in the same region. This paper investigates the use of profiling in a region-based compilation framework and measures its impact on the register allocation phase. The profiling information can be used by the register allocator to assign values to physical registers based on the execution frequency of the regions. Register allocation can be performed on the most frequently executed regions first so that any spilling that occurs causes memory accesses in less frequently executed regions. The experimental study indicates that profile assisted region formation and register allocation can result in code that executes faster than the code that was compiled without using profiling information and the amount of spill code executed can be reduced significantly.

24/7 lectures as an exam review technique

Assessment of student learning through tests, or examinations, is one of those necessary evils. No one seems to enjoy it, but everyone admits the necessity of it. Reducing student anxiety and frustration is an important activity to obtain a meaningful assessment of their learning. A common way for teachers to help students prepare is with a review session. This paper describes a structured review technique that actively engages every student in a multisensory way, requires little work on the part of the instructor, and is both entertaining and fun. Most important, this paper describes an empirical study that demonstrates the dramatic efficacy of the technique.

LC3uArch: a graphical simulator of the LC-3 microarchitecture

The small instruction set size of the LC-3 as well as its similarities to more powerful instruction sets make it an ideal hypothetical machine for introductory computer science and computer engineering students. Several tools are available for working with this hypothetical machine including simulators, and assemblers for various platforms. We have created an additional tool, LC3uArch, that is useful for debugging LC-3 programs like the existing simulators, but unlike existing simulators also helps student to develop an understanding of the LC-3 microarchitecture. The results of a student survey on the use of LC3uArch indicate our students find LC3uArch a valuable learning tool.

Blending object-oriented design principles and software engineering practices into an undergraduate architecture simulator project

It is well understood pedagogically that students learn better through active involvement. Thus the use of architecture simulators can enhance student learning in a computer organization, assembly programming, or architecture course. A deeper understanding can be attained by having students actually construct an architecture simulator. This paper describes the object-oriented design of a junior-level architecture course project that centers around the construction of a PDP-11 simulator. In addition, since this is a substantial system to build, the project blends in a number of software development practices designed to expose students in a practical and subtle way to valuable software engineering principles.

An experimental evaluation of a distributed Java compiler

For large programs consisting of many source files, the compilation process can be quite time consuming. For the C and C++ programming languages, there exists a program named distcc, the Distributed C Compiler [2], to facilitate the parallel compilation of source into machine code. This paper discusses our investigation into whether distributing the compilation of Java files can result in a faster compilation of large Java projects. The research indicates that the distributed compilation of projects consisting of a large number of relatively large source files can see a speed improvement over the traditional implementation of javac.