Claudia Hebedean

Minimization of the equivalent parallel capacitance in planar magnetic integrated structures

The magnetic planar technology is nowadays an attractive solution for designing the Electromagnetic Interference (EMI) filters due to its efficiency at high frequencies and its mechanical robustness. On the other hand, the general trend of reducing the dimensions of the integrated structures one inherently leads to the increase of their structural parasitic effects. Therefore, the minimization of the parasitic capacitances and inductances represents an important issue for increasing the performances of a magnetic integrated structure. In this light, the paper proposes a method for the minimization of the equivalent parallel capacitance (EPC) of these structures based on optimal design. The paper describes the optimization algorithm developed by the authors designed to determine the optimal placement of the structures conductor routes that minimize the structural inter-winding capacitance. In the first part of the paper the theoretical background is presented while in the second part the optimization algorithm validation and numerical examples are outlined, followed by the final conclusions.

Technologies to increase HF losses in planar structures and their limitations

Planar structures are often used in our days due to advantages like lower profile, lower leakage inductances and better thermal management. Although highly used components like power transformers, power inductors and EMI filters are built using this technique, planar structures must be improved because planar structure technology also has disadvantages like large footprint area, increased parasitic capacitance and low window utilization factor. In order to increase the efficiency of planar EMI filters, the equivalent parasitic capacitance (EPC) and the equivalent series inductance (ESL) must be eliminated and high frequency (HF) losses must be increased. This paper presents a study of technologies that can be used to increase HF losses in a planar structure and the parameters that affect the structures behavior.

Minimization of the equivalent parallel capacitance in planar magnetic EMI filters

The magnetic planar technology is nowadays an attractive solution for designing the electrical devices due to its efficiency at high frequencies and its mechanical robustness. On the other hand, the general trend of reducing the dimensions of the integrated structures one inherently leads to the increase of their structural parasitic effects. In this light, the paper proposes a new method for the minimization of the equivalent parallel capacitance (EPC) of these structures based on optimal design. The paper describes the optimization algorithm developed by the authors designed to determine the optimal placement of the structures conductor routes that minimize the structural inter-winding capacitance. In the first part of the paper the theoretical background is presented while in the second part the optimization algorithm validation and the usage of the OptimCond package for complex planar magnetic integrated structures are outlined, followed by the final conclusions.

Modeling and mitigation techniques of the magnetic integrated structures parasitic capacitance

The magnetic planar technology is nowadays an attractive solution for designing the Electromagnetic Interference (EMI) filters due to its efficiency at high frequencies and its mechanical robustness. On the other hand, the general trend of reducing the dimensions of the integrated structures one inherently leads to the increase of their structural parasitic effects. Therefore, the minimization of the parasitic capacitances and inductances represents an important issue for increasing the performances of a magnetic integrated structure. In this light, the aim of this paper is to present the authors contribution to developed structural parasitic capacitance reduction solutions from devices realized in planar magnetic technology. Being structures with an important geometrical complexity, the structural parasitic capacitance cannot be defined by direct calculation expressions and it cannot be localized in one device, it being practically distributed in the space between the coil wirings that form the structure. So, in this paper, are proposed approached techniques to reduce the structural parasitic capacitance in planar magnetic integrated structures.

Spiral inductors analysis and modelling

Spiral inductors are extensively used in micrometer modern integrated circuits. They find their applicability manly in telecommunication and communication with or without wire (wireless). We have been done many studies about spiral inductors. We have analyzed and modeled them. Then we have developed, designed and implemented two software programs dedicated to analyze spiral inductors in low and high frequency for micro and nanometer dimensions. In this paper we want to analyze and model square, hexagonal, octagonal and circular spiral inductors of micrometer dimensions using one of our software in order to optimize them and to improve their performances.

Parasitic capacitance removal with an embedded ground layer

One of the major goals in designing integrated EMI filters is to improve their high-frequency characteristics. To achieve this, special technologies need to be developed, including the mechanism for suppression of the equivalent parallel capacitance (EPC). In previous studies, there were several methods used to reduce this parasitic capacitance, but in this paper shifting and redistributing the energy stored between windings is the solution proposed. For planar structures, the way to put this method into practice is an embedded ground layer inserted between winding layers. The results contained in this paper present the influence of the embedded ground layer and its parameters on the structural winding capacitances.

Optimum geometry for planar structures regarding their loss factor

Planar structures are often used recently due to their many advantages. Transformers, power inductors and EMI filters are only a few components that are constructed using this technique. In order to increase their efficiency, parasitic capacitance (EPC) and equivalent series inductance (ESL) must be decreased and HF losses must be appropriate to their utilization. This paper represents a study which aims at finding how the shifting of the windings influences HF losses and also determining the optimum geometry for increasing the losses in planar structures.

The influence of parameters on the parasitic capacitance values in a planar transformer

Planar transformers are mainly used in power electronics but they can be also found in electric vehicles, medical applications, power sources, rectifiers and other devices. They have a lot of advantages like low profile, which leads to low core losses, higher efficiency, manufacturing repeatability, and reduced electromagnetic interferences. On the other side, there are a few aspects which must be improved like decreasing the parasitic capacitance between the windings and decreasing the losses in the structure. This paper focuses on the parasitic capacitance decrease in a planar transformer based on the constructive parameters variation.

Analysis of the influence of parasitic parameters on planar transformers

The use of planar transformers has increased in the last few years due to their efficiency in high frequency switching-mode power supplies (SMPS). Like all other devices constructed in planar technology, they have a lot of advantages like repeatability of elements, decreased dimensions and weight and high switching frequency, but there are some disadvantages too. In order to improve them one must know that the parasitic elements which must be suppressed are the parasitic capacitances between the windings, the leakage inductance and the losses. This paper analyzes the parasitic parameters of planar transformers, aiming to optimize them by the minimization of the losses and parasitic capacitances.

Filter geometry optimization for the conduction electromagnetic interferences suppression

The objective of this paper is to present how the filter geometry optimization for the electromagnetic interference suppression will lead to the improvement of its performances. In order to determine the optimal geometry of these filters, the authors developed and implemented an optimal design program intended to determine the optimal configuration of the structure for the case in which the parasitic effects are minimal. So, in the first part of the paper the design program developed by the authors will be presented and in the second part the effect of the filter geometry optimization on the structural parasitic capacitance minimization is determined. The paper will be ended with final conclusions.