Clement Wann

25 nm CMOS design considerations

This paper explores the limit of bulk (or partially-depleted SOI) CMOS scaling. A feasible design for 25 nm (channel length) CMOS, without continued scaling of oxide thickness and power supply voltage, is presented. A highly 2D nonuniform profile (super-halo) is shown to yield low off-currents while delivering a significant performance advantage for a 1.0 V power supply. Several key issues, including source-drain doping requirements, band-to-band tunneling, and poly depletion effects, are examined and quantified. It is projected, based on Monte-Carlo simulations, that the delay performance of 25 nm CMOS is 3/spl times/ higher than 100 nm CMOS, and that the nFET f/sub T/ exceeds 250 GHz.

A comparative study of advanced MOSFET concepts

Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has been the major device for integrated circuits over the past two decades. With technology advancement, there have been numerous MOSFET structures for channel length of 0.1 /spl mu/m and below reported in industrial research. A side-by-side comparison of these advanced device structures can provide useful understanding in device physics and the design tradeoffs among MOSFETs parameters. In this work we employ experimental data, device simulation, and analytical modeling for device comparison. The devices were developed at several different research laboratories. Guided by experimental data and simulations, analytical models for topics such as threshold voltage, short-channel effect, and saturation current for these different MOSFET structures are developed. These analytical models are then used for optimizing each device structure and comparing the devices under the same set of constraints for a fair comparison. The key design parameters are highlighted and the strength and weakness of each device structure in various performance categories are discussed.

SRAM cell design for stability methodology

SRAM stability during word line disturb (access disturb) is becoming a key constraint for V/sub DD/ scaling (Burnett, 1994). In this paper we present a design methodology for SRAM stability during access disturb. In this methodology, the SRAM access disturb margin (ADM) is defined as the ratio of the magnitude of the critical current to maintain SRAM stability (I/sub CRIT/) to the sigma of I/sub CRIT/. Using ADM as a figure of merit, this methodology enables one to project the cell stability margin due to process variations, e.g. V/sub T/ variation, during design of a SRAM cell. Using statistical analysis, the required stability margin for an application requirement such as array size and available redundancy can be estimated. Direct cell probing and array test can be used to verify that the stability target is met.

Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET

In this work device design of DTMOS and its parasitic components are studied by experiments and simulations. The gate and the body are tied at the side of the device. Similar gate-body tie can also be accomplished in bulk substrate using multiple-well technology. For a circuit whose speed is predominately determined by wiring capacitances, DTMOS can greatly enhance performance by engineering the vertical doping profiles to scale the depletion width. When the circuit speed is dominated by device capacitances, lateral doping engineering is important to reduce Cbs and Cbd in order to obtain performance improvements, especially in certain logic circuits where Miller effect is important.

High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

A leading edge 90 nm logic bulk foundry technology with 45 nm gate length devices, incorporating strain engineering, is described in this paper. Gate length and dielectric scaling, along with optimized strain engineering, enable high performance devices, which are amongst the best reported to date. Short channel effect control down to 35 nm is demonstrated. Both NMOS and PMOS performance are improved through careful optimization of stress effects from both trench isolation and contact etch stop nitride film. Furthermore, analysis of the channel mobility and current enhancement is used to gain understanding of the stress mechanisms, and hence layout design practice should be optimized for performance.

High performance and low power transistors integrated in 65nm bulk CMOS technology

This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated an astonishing 35 % performance enhancement from the previous technology node

An AC conductance technique for measuring self-heating in SOI MOSFET's

In this paper, we present a new technique for isolating the electrical behavior of an SOI MOSFETs from the self-heating effect using an AC conductance method. This method reconstructs an I-V curve by integrating high frequency output conductance data. The heating effect is eliminated when the frequency is much higher than the inverse of the thermal time constant of the SOI device. We present measurement results from SOI MOSFETs that demonstrate that heating can indeed be significant in SOI devices.<<ETX>>

CMOS with active well bias for low-power and RF/analog applications

We show that with a forward body bias, CMOS performance can be improved for those applications which are primarily concerned with speed, and for those which have fixed performance targets but desire lower switching energy (higher MHz/mW). Thus V/sub t/ can be set according to standby power requirement or device design (well and halo engineering), forward body bias is then applied to improve speed or to reduce active power. No compromise in I/sub off/ results if the forward bias is applied when the circuits are active, during which time I/sub off/ and the leakage current are small compared to the switching current. Therefore a low-power CMOS strategy should use a MOSFET as a four-terminal device with a fast top gate and a slow bottom gate shared by a block. Deep-trench isolation with STI provides fine-grain isolation for body bias blocks without area penalty. Making the body available also improves the device analog properties and enables new applications. We present an active-well VCO/mixer as an example.

Design and Fabrication of MOSFETs with a Reverse Embedded SiGe (Rev. e-SiGe) Structure

A novel device structure containing a SiGe stressor is used to impose tensile strain in nMOSFET channel. 400MPa of uniaxial tensile stress is induced in the Si channel through elastic relaxation/strain of the SiGe/Si bi-layer structure. This strain results in 40% mobility enhancement and 15% drive current improvement for sub-60nm devices compared to the control device with no strain

Mechanism of Threshold Voltage Shift (ΔVth) Caused by Negative Bias Temperature Instability (NBTI) in Deep Submicron pMOSFETs

The physical mechanism responsible for negative bias temperature instability (NBTI), which is basic to the minimization of this degradation mode, is investigated, and an analytical model is developed accordingly. Experiments with 1.7 nm to 3.3 nm gate dielectrics fabricated by different processes demonstrate the capability of the proposed model.