Clemente Rodríguez

Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems

In multitasking real-time systems it is required to compute the WCET of each task and also the effects of interferences between tasks in the worst case. This is very complex with variable latency hardware, such as instruction cache memories, or, to a lesser extent, the line buffers usually found in the fetch path of commercial processors. Some methods disable cache replacement so that it is easier to model the cache behavior. The difficulty in these cache-locking methods lies in obtaining a good selection of the memory lines to be locked into cache. In this paper, we propose an ILP-based method to select the best lines to be loaded and locked into the instruction cache at each context switch (dynamic locking), taking into account both intra-task and inter-task interferences, and we compare it with static locking. Our results show that, without cache, the spatial locality captured by a line buffer doubles the performance of the processor. When adding a lockable instruction cache, dynamic locking systems are schedulable with a cache size between 12.5% and 50% of the cache size required by static locking. Additionally, the computation time of our analysis method is not dependent on the number of possible paths in the task. This allows us to analyze large codes in a relatively short time (100KB with 10^6^5 paths in less than 3min).

Low cost parallel solutions for the VRPTW optimization problem

In the paper a parallelizable system based on simulated annealing to solve vehicle routing problem with time window (VRPTW) problems is described. The system consists of two optimization phases: a global one, and local one, both based on simulated annealing and parallizable. For the first phase different parallelization strategies are presented and evaluated. The importance of the co-operation among processors has been made clear: the communication of partial solutions improves the efficiency of optimal solutions search. Two algorithms, a synchronous one and an asynchronous one, stand out due to their good average behaviour related to the quality of solutions found, and due to their stability when augmenting the number of processors. The second phase has shown to be a great complement of the global search that permits to obtain a very fast and practical, low cost parallel system. This system has been able to reach the optimal solution published for the Solomons benchmark in an 85% of the problems, and more important, the averages of any set of random executions are less than 5% worse than the best published.

A two-stage classifier for broken and blurred digits in forms

A classifier for an automatic system that recognizes multifont typewritten digits, often broken and blurred, in forms is presented. The classification, which is based on the utilization of a global feature, is applied in two phases. Firstly, a minimum distance method (1-NN) is applied in a multifont classifier to provide a global classification of the patterns in a form. A problem associated to multifont classifiers is the interference among classes in different fonts. An interesting aspect of this particular application is that it is highly probable that a form includes just one font. Then, in the second phase, a specialized classifier, oriented to one-form, uses the patterns in the form previously classified to validate, or reject and reclassify them, on the basis of the mean distance to the predefined classes. This specialized classifier affords significant improvement in performance. A classification accuracy rate of 99.42% has been achieved.

Low cost parallel solutions for the VRPTW optimisation problem

In this paper, a two phase system (global optimisation and local optimisation) to solve VRPTW problems is described; both phases are based on Simulated Annealing and parallelised. For the first phase, different parallelisation strategies are presented and evaluated. Two algorithms, a synchronous one and an asynchronous one, stand out due to their good average behaviour. The second phase permits very fast improvement of the solutions, adding efficiency to the system. This system has been able to reach the optimal solution published for the Solomons benchmark in 85% of the problems, and more importantly, the averages of any set of random executions are less than 5% inferior to the best published.

Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems

In multitasking real-time systems it is required to compute the WCET of each task and also the effects of interferences between tasks in the worst case. This is complex with variable latency hardware usually found in the fetch path of commercial processors. Some methods disable cache replacement so that it is easier to model the cache behavior. Lock-MS is an ILP based method to obtain the best selection of memory lines to be locked in a dynamic locking instruction cache. In this paper we first propose a simple memory architecture implementing the next-line tagged prefetch, specially designed for hard real-time systems. Then, we extend Lock-MS to add support for hardware instruction prefetch. Our results show that the WCET of a system with prefetch and an instruction cache with size 5% of the total code size is better than that of a system having no prefetch and cache size 80% of the code. We also evaluate the effects of the prefetch penalty on the resulting WCET, showing that a system without prefetch penalties has a worst-case performance 95\% of the ideal case. This highlights the importance of a good prefetch design. Finally, the computation time of our analysis method is relatively short, analyzing tasks of 96 KB with 10^65 paths in less than 3 minutes.

Fault analysis with modular neural networks

Abstract Automatic fault diagnosis in power systems presents real challenges to computing technologies. As an alternative approach to expert systems, several neural network solutions have been proposed recently. In this paper a modular, neural network-based solution to power systems alarm handling and fault diagnosis is described that overcomes the limitations of ‘toy’ alternatives constrained to small and fixed-topology electrical networks. In contrast to monolithical diagnosis systems, the neural network-based approach presented here fulfills the scalability and dynamic adaptability requirements of the application. Mapping the power grid onto a set of interconnected modules that model the functional behaviour of electrical equipment provides the flexibility and speed demanded by the problem. The way in which the neural system is conceived allows full scalability to real-size power systems.

COMPARISON OF SYSTEMS BASED ON EVOLUTIONARY SEARCH AND SIMULATED ANNEALING TO SOLVE THE VRPTW PROBLEM

This paper presents the design and analysis of several systems to solve Vehicle Routing Problems with Time Windows (VRPTW) limiting the search to a small number of solutions explored. All of them combine a metaheuristic technique with a route building heuristic. Simulated Annealing, different evolutionary approaches and hybrid methods have been tried. Preliminary results for each of the strategies are presented in the paper, where the combination created by some iterations of the best evolutionary approach and some iterations of SA stands out. A more exhaustive analysis of the three methods behaving better is also presented confirming the previous results. The different strategies have been implemented and tested on a series of the well-known Solomons benchmark problems of size up to 100 customers. One of the described systems combined with a local optimization part that tries to optimize parts of a solution is being used as part of a real oil distribution system, obtaining very satisfactory results for the company.

An incremental and hierarchical k-NN classifier for handwritten characters

This paper analyses the application of hierarchical classifiers based on the k-NN rule to the automatic classification of handwritten characters. The discriminating capacity of a k-NN classifier increases as the size of the reference pattern set (RPS) increases. This supposes a problem for k-NN classifiers in real applications: the high computational cost required when the RPS is large. In order to accelerate the process of calculating the distance to each pattern of the RPS, some authors propose the use of condensing techniques. These methods try to reduce the size of the RPS without losing classification power. Our alternative proposal is based on incremental learning and hierarchical classifiers with rejection techniques that reduce the computational cost of the classifier. We have used 133,944 characters (72,105 upper-case characters and 61,839 lower-case characters) of the NIST Special Data Bases 3 and 7 as experimental data set. The binary image of the character is transformed to a gray image. The best non-hierarchical classifier achieves a hit rate of 94.92% (upper-case) and 87,884% (lower-case). The hierarchical classifier achieves the same hit ratio, but with 3 times lower computational cost than the cost of the best non-hierarchical classifier found in our experimentation and 14% less than Harts (1968) algorithm.

Multidimensional multistage k-NN classifiers for handwritten digit recognition

This paper analyses the application of multistage classifiers based on the k-NN rule to the automatic classification of handwritten digits. The discriminating capacity of a k-NN classifier increases as the size and dimensionality of the reference pattern set (RPS) increases. This supposes a problem for k-NN classifiers in real applications: the high computational cost required. In order to accelerate the process of calculating the distance to each pattern of the RPS, some authors propose the use of condensing techniques. These methods try to reduce the size of the RPS without losing classification power. Our alternative proposal is based on hierarchical classifiers with rejection techniques and incremental learning that reduce the computational cost of the classifier. We have used 270,000 digits (160,000 digits for training and 110, 000 for the test) of the NIST Special Data Bases 19 and 3 (SD19 and SD3) as experimental data sets. The best non -hierarchical classifier achieves a hit rate of 99.50%. The hierarchical classifier achieves the same hit ratio, but with 24.5 times lower computational cost than best non-hierarchical classifier found in our experimentation and 6 times lower than Harts Algorithm.

Hierarchical classifiers based on neighbourhood criteria with adaptive computational cost

Classifiers based on neighbourhood concept require a high computational cost when the Reference Patterns Set is large. In this paper, we propose the use of hierarchical classifiers to reduce this computational cost, maintaining the hit rate in the recognition of handwritten digits. The hierarchical classifiers reach the hit rate of the best individual classifier. We have used NIST Database to carry out the experimentation, and we have worked with two test sets: in Test 1 (SD3, SD19) the hit rate is 99.54%, with a speed-up of 40.6, and in Test 2 (SD7), the hit rate is 97.51% with a speed-up of 15.7.