Conal E. Murray

High-mobility ultrathin semiconducting films prepared by spin coating.

The ability to deposit and tailor reliable semiconducting films (with a particular recent emphasis on ultrathin systems) is indispensable for contemporary solid-state electronics. The search for thin-film semiconductors that provide simultaneously high carrier mobility and convenient solution-based deposition is also an important research direction, with the resulting expectations of new technologies (such as flexible or wearable computers, large-area high-resolution displays and electronic paper) and lower-cost device fabrication. Here we demonstrate a technique for spin coating ultrathin (∼50 Å), crystalline and continuous metal chalcogenide films, based on the low-temperature decomposition of highly soluble hydrazinium precursors. We fabricate thin-film field-effect transistors (TFTs) based on semiconducting SnS2-xSex films, which exhibit n-type transport, large current densities (>105 A cm-2) and mobilities greater than 10 cm2 V-1 s-1—an order of magnitude higher than previously reported values for spin-coated semiconductors. The spin-coating technique is expected to be applicable to a range of metal chalcogenides, particularly those based on main group metals, as well as for the fabrication of a variety of thin-film-based devices (for example, solar cells, thermoelectrics and memory devices).

Liner materials for direct electrodeposition of Cu

We identified a family of materials which can be directly electroplated with Cu in acidic plating baths commonly found in the microelectronics industry. Details are presented illustrating a number of important properties of the electroplated Cu/linear material system. These include the adhesion of the plated film to liner material, the recrystallization behavior of the plated film, the texture of the plated film, and the resistivity of the plated film after high-temperature anneals. Finally, an example is presented illustrating the direct plating of Cu across an 8 in. wafer without the use of a Cu seed layer.

Sharp Reduction of Contact Resistivities by Effective Schottky Barrier Lowering With Silicides as Diffusion Sources

An extremely low contact resistivity of 6-7 × 10^-9 Ω·cm² between Ni_0.9Pt_0.1Si and heavily doped Si is achieved through Schottky barrier engineering by dopant segregation. In this scheme, the implantation of B or As is performed into silicide followed by a low-temperature drive-in anneal. Reduction of effective Schottky barrier height is manifested in the elimination of nonlinearities in IV characteristics.

Elastic strain relaxation in free-standing SiGe/Si structures

We have investigated elastic strain relaxation, i.e., strain relaxation without the introduction of dislocations or other defects, in free-standing SiGe/Si structures. We fabricated free-standing Si layers supported at a single point by an SiO2 pedestal and subsequently grew an epitaxial SiGe layer. The measured strain relaxation of the SiGe layer agrees well with that calculated using a force-balance model for strain sharing between the SiGe and strained Si layers. We report strained Si layers with biaxial tensile strain equal to 0.007 and 0.012.

High-resolution strain mapping in heteroepitaxial thin-film features

Heteroepitaxial thin-film features that are lattice matched to the underlying substrate undergo elastic relaxation at the free edges of the feature. To characterize the degree of elastic relaxation, we employed synchrotron-based x-ray diffraction techniques to map the change in lattice spacing in the thin film at a submicron resolution. Measurements were conducted on 0.24‐μm thick, heteroepitaxially grown SiGe strips of various widths on Si (001). A comparison of the SiGe diffraction peak positions across the features provides a real-space mapping of the extent of elastic relaxation as a function of linewidth. The resultant in-plane normal film stress measurements were compared to calculated values from several elastic mechanical models to assess their validity in predicting stress distributions within the features.

32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches

Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel data analysis is shown to be important for hardness assurance where Monte Carlo modeling with a realistic heavy ion track structure, along with a new visualization aid (the Angular Dependent Cross-section Distribution, ADCD), allows one to quickly assess the improvements, or limitations, of a particular latch design. It was found to be an effective technique for making SEU predictions for alternative 32 nm SOI latch layouts.

Finite size effects in stress analysis of interconnect structures

Conventional formulations of thermal stress evolution in interconnect structures usually ignore the interface integrity between the various levels. In this letter we present thermal and residual stress versus temperature data from simple copper thin-film structures on silicon. The results indicate that interconnection models which assume fully elastic behavior and perfectly bonded interfaces may yield inaccurate predictions of the thermo-mechanical response for feature sizes smaller than 10μm.

Mapping of strain fields about thin film structures using x-ray microdiffraction

Substrate distortions were mapped near pseudomorphically grown SiGe thin film etched lines of various widths from 1.5 to 20 μm on Si(001) and 190 μm diameter Ni dots on Si(111) using reflection x-ray microdiffraction topography. The strain field extended 30–120 times the thickness of the film away from the feature edge. The profile of the enhanced diffracted intensity was found to follow a characteristic curve when the distance from the feature edge is normalized by a mean interaction distance that depends on the feature size. This normalization and the observed strain decay profiles cannot be predicted or modeled using existing micromechanical models.

A Rigorous Comparison of X-ray Diffraction Thickness Measurement Techniques using Silicon-on-insulator Thin Films

Thickness data from semiconductor-grade silicon-on-insulator thin-film samples determined from high-resolution X-ray diffraction (HRXRD) data using the Scherrer equation, rocking-curve modeling, thickness fringe analysis, Fourier analysis and the Warren–Averbach method, as well as with cross-sectional transmission electron microscopy and X-ray reflectivity measurements, are presented. The results show that the absolute accuracy of thin-film thickness values obtained from HRXRD data is approximately 1 nm for all techniques if all sources of broadening are correctly identified, while their precision is one or two orders of magnitude smaller. The use of multiple techniques is required to determine the various contributions to peak broadening.

Submicron mapping of silicon-on-insulator strain distributions induced by stressed liner structures

Strain distributions within a silicon-on-insulator (SOI) layer induced by overlying compressively stressed Si3N4 features were measured using x-ray microbeam diffraction. A comparison of analytical and numerical mechanical models of the depth-averaged strain distributions to the measured strain profiles in the SOI layer indicated a blanket film stress of −2.5 GPa in the Si3N4 features. A two-dimensional boundary element model, implemented to analyze thin film/substrate systems, reproduced the observed strain distributions better than an edge-force formulation due to the incorporation of loading along the Si3N4/Si interface.