Constantin Anton

Detecting errors in digital communications with CRC codes implemented with FPGA

Generally speaking, cyclic redundancy checks (CRCs) are used to detect errors from noise in digital data transmission. The technique is also sometimes applied to data storage devices, such as a disk drive. They also have been turned to verify the integrity of files in a system in order to prevent tampering and suggested as a possible algorithm for manipulation detection codes. It has been known that a CRC will not detect all errors but with random noise it is unlikely. In this paper, we present an efficient algorithm for parallel computation of the CRC in data transmission.

Error detection and correction using LDPC in parallel Hopfield networks

Low Density Parity Check (LDPC) coding is a classical method for the detection and correction of errors. Its problem is the relatively complex operations which must be performed at encoding, and especially at decoding, to detect and correct errors caused by communication channels. We present a solution for the errors correction using regular LDPC and Hopfield network-based associative memories. Our solution solves this problem by using an associative memory based on the Hopfield network on the decoding stage, which stores the correct code words. This memory tends to transform the code words received with errors in errors free code words. We improved the ability of the associative memory by storing the code words in a specific format (pairs with their inverses, the constant number of “1” bits). These conditions are met by using LDPC coding. To be viable in communications, which require real-time correction, our proposed solution has used Hopfield networks operating in parallel, fully integrated into the Field Programmable Gates Array (FPGA) circuit.