Constantinos Efstathiou

An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator

Complex arithmetic operations are widely used in Digital Signal Processing (DSP) applications. In this work, we focus on optimizing the design of the fused Add-Multiply (FAM) operator for increasing performance. We investigate techniques to implement the direct recoding of the sum of two numbers in its Modified Booth (MB) form. We introduce a structured and efficient recoding technique and explore three different schemes by incorporating them in FAM designs. Comparing them with the FAM designs which use existing recoding schemes, the proposed technique yields considerable reductions in terms of critical delay, hardware complexity and power consumption of the FAM unit.

On the Design of Modulo 2^n+1 Multipliers

In this work a new efficient modulo 2n+1 modified Booth multiplication algorithm for operands in the weighted representation is proposed. According to our algorithm n/2+2 partial products are derived. The resulting partial products are reduced by an inverted end around carry save adder tree to two operands, which are finally added by a diminished-1 modulo 2n+1 adder. Our design compares favorably for both area and delay to the modulo 2n+1 modified Booth multipliers previously proposed.

Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding

In this work a new efficient modulo 2^n+1 modified Booth multiplication algorithm for both operands in the weighted representation is proposed. Furthermore, the same algorithm is extended to realize modulo 2^n+1 multiply-add units. The derived partial products are reduced by an inverted end around carry-save adder tree to two operands, which are finally added by a modulo 2^n+1 adder. The performance and efficiency of the proposed multipliers are evaluated and compared against the earlier modulo 2^n+1 multipliers, based on a single gate level model. Comparisons based on experimental CMOS implementations for both the multiply and multiply-add units are also given. The proposed multipliers yield area and power savings by an average of 15% and 10% respectively, while the corresponding area and power savings of the proposed multiply-add units are 14% and 21% respectively.

Fused modulo 2 n − 1 add-multiply unit

Complex arithmetic operations are widely used in Digital Signal Processing (DSP) applications. Targeting to increase performance, in this work, we focus on optimizing the design of the modulo 2n - 1 Add-Multiply (AM) operation. We incorporate in the design the direct recoding of the sum of two numbers in its Modified Booth (MB) form. Compared to the conventional design of first instantiating a modulo 2n - 1 adder and then, driving its output to a modulo 2n - 1 multiplier, the proposed fused AM design yields considerable reductions in terms of critical delay, area complexity and power consumption.

Modulo 2n ± 1 Fused Add-Multiply Units

Complex arithmetic operations are widely used in Digital Signal Processing (DSP) applications. Targeting to increase performance, in this work, we focus on optimizing the design of the modulo 2n ± 1 Add-Multiply (AM) operation. The proposed modulo 2n ± 1 fused AM units incorporate an initial row of Half Adders which carry out the requested addition of two specified operands resulting to an intermediate Delayed Carry representation of their sum. The Delayed Carry represented vectors are then multiplied by the specified multiplicand and the partial products are driven to OR logic gates in pairs. Using the appropriate Carry-Save (CS) Adder trees, the resulting n-bit operands are reduced to a pair of CS vectors, which are finally added by a modulo 2n -- 1 or a modulo 2n + 1 adder. Compared to the conventional designs of first instantiating a modulo 2n ± 1 adder and then, driving its output to a modulo 2n ± 1 multiplier, the proposed fused AM designs yield considerable reductions in terms of critical delay, area complexity and power consumption.

Modulo 2 n +1 addition and multiplication for redundant operands

Complex arithmetic operations are widely used in Digital Signal Processing (DSP) applications. Keeping the intermediate results in a redundant representation (e.g. carry-save) is a common technique to speed up chained arithmetic operations due to the elimination of the intermediate parallel additions which occupy significant area and largely increase the overall critical delay. Thus, arithmetic units with operands in a redundant representation are of considerable practical interest. In this work, we propose an efficient modulo 2n+1 addition unit with one or both operands in the redundant carry-save representation and, also, we introduce an efficient modulo 2n+1 multiplier with the one of two operands in the redundant carry-save form.

On the design of modulo 2 n ±1 residue generators

In this paper, we propose an efficient residue generator which concurrently computes the residues modulo 2ⁿ+1 and modulo 2ⁿ-1. The input operands are divided into n-bit vectors which are then grouped into two sets and added by two separate Carry Save Adder (CSA) trees. The output carry of each stage of the first CSA tree is used as input to the corresponding stage of the second CSA tree, while the output vectors of the trees are finally added modulo 2ⁿ+1 and 2ⁿ-1 to compute the residues. The proposed residue generator is well suited for Residue Number System (RNS) based applications which use both modulo 2ⁿ+1 and 2ⁿ-1 residues. An efficient configurable modulo 2ⁿ±1 residue generator is also proposed.

On the Design of Configurable Modulo 2n±1 Residue Generators

In this work new efficient modulo 2ⁿ+1 residue generators are proposed. The input operands are divided into n-bit vectors which are added by an inverted end around carry save adder tree and a final stage diminished-1 modulo 2ⁿ+1 adder. The conversion of the proposed residue generators to configurable modulo 2ⁿ±1 ones is also discussed. Modulo 2ⁿ±1 residue generators find applicability as forward converts from the binary to the residue number system, and in the design of self-checking digital systems.

Fused modulo 2n + 1 Add-Multiply unit for diminished-1 operands

Complex arithmetic operations dominate Digital Signal Processing (DSP) applications heavily degrading their performance. Targeting to accelerate the Residue Number Systems-based DSP applications, we optimize the design of the Add-Multiply (AM) operation with modulo 2n + 1 diminished-1 operands by incorporating the direct recoding of the sum of two numbers in its Modified Booth form. Compared to the conventional allocation of an adder and a subsequent multiplier, the proposed fused AM design yields delay, area and power gains.

Fused modulo 2n + 1 add-multiply unit for weighted operands

Digital Signal Processing (DSP) applications are dominated by complex arithmetic operations, which heavily degrade their performance. Targeting to accelerate the execution of Residue Number Systems (RNS)-based DSP applications, in this work, we focus on optimizing the design of the modulo 2n + 1 Add-Multiply (AM) operation with weighted operands. We incorporate in our design a new direct recoding of the modulo 2n + 1 sum of two weighted operands in its Modified Booth form. Compared to the conventional design of first instantiating an adder and then, driving its output to a multiplier, the proposed fused AM design yields considerable delay, area and power gains.