Corneliu A. Marinov

Another K-winners-take-all analog neural network

An analog Hopfield type neural network is given, that identifies the K largest components of a list of d of N real numbers. The neurons are identical, with a tanh characteristic, and the weight matrix is symmetric and fully filled. The list to be processed is a summand of the input currents of the neurons, and the network is started from zero. We provide easily computable restrictions on the parameters. The main emphasis here is on the magnitude of the neuronal gain. A complete mathematical analysis is given. The trajectories are shown to eventually have positive components precisely in the positions given by the K largest elements in the input list.

Performance analysis for a K-winners-take-all analog neural network: basic theory

In a previous work, the authors proposed an analog Hopfield-type neural network that identified the K largest components of a list of real numbers. In this work, we identify computable restrictions on the parameters, in order that the network can repeatedly process lists, one after the other, at a given rate. A complete mathematical analysis gives analytical bounds for the time required in terms of circuit parameters, the length of the lists, and the relative separation of list elements. This allows practical setting of circuit parameters for required clocking times. The emphasis is on high gain functioning of each neuron. Numerical investigations show the accuracy of the theoretical predictions, and study the influence of various parameters on performance.

Mathematical Models in Electrical Circuits: Theory and Applications

I. Dissipative operators and differential equations on Banach spaces.- 1.0. Introduction.- 1.1. Duality type functionals.- 1.2. Dissipative operators.- 1.3. Semigroups of linear operators.- 1.4. Linear differential equations on Banach spaces.- 1.5. Nonlinear differential equations on Banach spaces.- II. Lumped parameter approach of nonlinear networks with transistors.- 2.0. Introduction.- 2.1. Mathematical model.- 2.2. Dissipativity.- 2.3. DC equations.- 2.4. Dynamic behaviour.- 2.5. An example.- III. lp-solutions of countable infinite systems of equations and applications to electrical circuits.- 3.0. Introduction.- 3.1. Statement of the problem and preliminary results.- 3.2. Properties of continuous lp-solutions.- 3.3. Existence of continuous lp-solutions for the quasiautonomous case.- 3.4. Truncation errors in linear case.- 3.5. Applications to infinite circuits.- IV. Mixed-type circuits with distributed and lumped parameters as correct models for integrated structures.- 4.0. Why mixed-type circuits?.- 4.1. Examples.- 4.2. Statement of the problem.- 4.3. Existence and uniqueness for dynamic system.- 4.4. The steady state problem.- 4.5. Other qualitative results.- 4.6. Bibliographical comments.- V. Asymptotic behaviour of mixed-type circuits. Delay time predicting.- 5.0. Introduction.- 5.1. Remarks on delay time evaluation.- 5.2. Asymptotic stability. Upper bound of delay time.- 5.3. A nonlinear mixed-type circuit.- 5.4. Comments.- VI. Numerical approximation of mixed models for digital integrated circuits.- 6.0. Introduction.- 6.1. The mathematical model.- 6.2. Construction of the system of FEM-equations.- 6.2.1. Space discretization of reg-lines.- 6.2.2. FEM-equations of lines.- 6.3. FEM-equations of the model.- 6.4. Residual evaluations.- 6.5. Steady state.- 6.6. The delay time and its a-priori upper bound.- 6.7. Examples.- 6.8. Concluding remarks.- Appendix I.- List of symbols.- References.

A theory of electrical circuits with resistively coupled distributed structures: delay time predicting

Qualitative properties (existence, uniqueness, and especially, stability) and numerical solution of a circuit consisting of a resistive multiport with r-c-g exactly modeled distributed elements connected to its terminals, are studied. These results are useful, for instance, when the effects of interconnections on the speed of the transient process in an integrated structure are studied. A formula to evaluate the delay time as a global parameter of the circuit is given and verified by numerical calculus. >

Time-Oriented Synthesis for a WTA Continuous-Time Neural Network Affected by Capacitive Cross-Coupling

A continuous time neural network built with nonlinear amplifiers which selects the largest item of a list (WTA) is considered. The network receives and processes lists admitted one by one. If the processing and resetting times are imposed, our paper gives a method to find the circuit parameters assuring a correct operation. We take into account the capacitive coupling between input terminals and present complete existence and convergence results on the differential model. The main achievement consists of simple bounds for the processing and resetting times. They are inferred by an original method of decoupling the system model into solvable linear differential inequalities. Also, a new procedure to impose the stationary WTA state is given. All these results are valid under various parameter restrictions. They lead to a neat design procedure which starts from imposed processing and resetting time and list density to determine the WTA threshold, the interconnection conductance, the amplifier gain, the bias current. Numerical examples check and interpret the results.

Iteratively improved bounds for RC circuits

For the waveform relaxation iterative process, the starting vectors can be found such that the iterations are globally monotonous, decreasing, or increasing. The method is new, and the class of RC circuits that we deal with is larger than in previous works.

Transient bounding in networks with distributed and lumped parameters

For a general network with distributed parameter lines (described by telegraph equations) with nodes grounded by RC lumped elements, upper and lower bounds of voltage at any point are given. Thus, the problem of bounding the delay time in such networks comes to solve a system of nonlinear algebraic inequalities. For tree-type circuits, we give two algorithms, doing this rapidly and providing reasonable tight bounds. The results are of interest for timing analysis of MOS interconnection structures.

Bounds for distributed parameter trees

The interconnection wires in VLSI circuits are modelled by telegraph equations. Upper and lower bounds are given for node voltages of a tree network composed of such wires and ended in lumped capacitors. These bounds are easily computable from circuit parameters and are sufficiently tight to be used in initial design stages of digital circuits.<<ETX>>

A delay time bound for distributed parameter circuits with bipolar transistors

We prove here a stability theorem concerning a parabolic system of equations with non-linear boundary conditions that governs the behaviour of a class of networks in which the bipolar transistors operating under large-signal conditions are interconnected with reg-lines modelled by telegraph equations

Mixed-type circuits with distributed and lumped parameters

The authors deal with qualitative properties of a large class of circuits in which the distributed-parameter rcg lines and lumped capacitors are connected by a linear resistive lumped multiport. They prove that for a large variety of time varying sources (of engineering significance), for inconsistent and nonsmooth initial conditions, and for a resistive multiport described by a positive definite matrix, it is possible to define precisely a solution of the mathematical model and to assure that this solution is unique, depends continuously on initial conditions and sources and has an asymptotic stability property. >