Costa Gerousis

Toward nanoelectronic cellular neural networks

We investigate the use of nanoelectronic structures in cellular nonlinear network (CNN) architectures, for potential application in future high-density and low-power CMOS-nanodevice hybrid circuits. We first investigate compact models for simulation of Single Electron Tunneling (SET) transistors appropriate for use in coupled SET-CMOS circuits. We then discuss simple CNN linear architectures using a SET inverter topology as the basis for the nonlinear transfer characteristic of individual cells. This basic SET CNN cell acts as a summing node, which is capacitively coupled to the inputs and outputs of nearest neighbor cells. Monte Carlo simulation results are then used to show CNN like behavior in attempting to realize different functionality such as a connected component detector and shadowing. Toward nanoelectronic cellular neural networks (PDF Download Available). Available from: http://www.researchgate.net/publication/228610387_Toward_nanoelectronic_cellular_neural_networks [accessed Jul 21, 2015].

Nanoelectronic single-electron transistor circuits and architectures

Single-electron tunneling (SET) devices have been proposed as one promising candidate for future nanoelectronic integrated circuits. SETs have appealing properties for implementing ultra-dense and complex signal and image processing systems. The potential for very dense arrays of SET transistors makes them attractive for the realization of cellular non-linear network (CNN) circuits, where locally-connected cells may alleviate the interconnect problem facing conventional architectures as they scale. Herein, we investigate the use of nanoelectronic structures in CMOS-type digital circuits and in analog CNN architectures for potential application in future high-density and low-power CMOS-nanodevice hybrid circuits. We first present an overview of the operation of the SET transistor and simulation of SET circuits. We then discuss a programmable CMOS-type SET logic circuit based on a summing-node-inverter structure, followed by simple linear and 2-d SET-CNN architectures using the SET inverter topology as the basis for the non-linear transfer characteristics required of individual CNN elements. The simple SET-CNN cell acts as a summing node that is capacitively coupled to the inputs and outputs of nearest neighbour cells. Monte Carlo simulation results are then used to show CNN-like behaviour in attempting to realize different functionality such as shadowing, pattern forming, and horizontal-line detection. Within the context of these simple architectures, we discuss the speed and signal delay in SET non-linear circuits, and calculate the approximate power dissipation in a SET network. Copyright

Modeling nanoelectronic CNN cells: CMOS, SETs and QCAs

Summary form only given, as follows. We investigate the use of nanoelectronic structures in cellular neural network (CNN) architectures, for future high-density and low-power CMOS-nanodevice hybrid circuits. We present simulation results for Single Electron Tunneling (SET) transistors configured as a voltage-to-current transducer for CNN cells. We also present an example of quantum-dot cellular arrays which may be used to realize binary CNN algorithms. Nanoelectronics offers the promise of ultra-low power and ultra-high integration density. Several device structures have been proposed and realized experimentally, yet the main challenge remains the organization of these devices in new circuit architectures. Here, we investigate the use of nanodevices in CNN architectures. Specifically, we focus on nanostructures based on SET devices and Coulomb-coupled quantum-dot arrays, the so-called Quantum-Dot Cellular Automata (QCA). CNN-type architectures for nanostructures are motivated by the following considerations: on the one hand, locally-interconnected architectures appear to be natural for nanodevices where some of the connectivity may be provided by direct physical device-device interactions. On the other hand, CNN arrays with sizes on the order of 1000-by-1000 (which are desirable for applications such as image processing) will require the use of nanostructures since such integration densities are beyond what can be achieved by scaling conventional CMOS devices.

Programmable logic arrays in single-electron transistor technology

This paper presents a programmable logic array (PLA) layered structure composed of single-electron tunneling transistor (SET) devices. In this array bits of information are represented by the presence or absence of single electrons at conducting islands. A layer in the array is composed of a SET summing-inverter cell replicated for performing a programmable Boolean operation of its inputs. A number of layers are added on to implement the logic function. We confirm the correct and stable operation of the PLA matrix using a well-known single-electron circuit simulator based on Monte Carlo technique. We then discuss challenges facing SETs and end with conclusions.

Nanoelectronic single-electron transistor circuits and architectures: Research Articles

Nanotechnology finds in flagellar bacteria an uncomparable example of a very efficient and miniaturized motor. This and the complex behaviour of the bacteria colonies growth in a self-organized way make the study of flagellar bacteria very important and appealing for possible applications. This brief paper presents an innovative point of view: instead of designing nanoscale devices the control of flagellar bacteria is an alternative solution for nanoscale problems. For these reasons in this work single bacterium motion and colonies growth have been studied by applying non-linear methods in order to characterize their behaviour and control it. The characterization of the single bacterium motion leads to the conclusion that determinism (due to chemotaxis) is predominant with respect to random terms. This result is confirmed by the possibility of modelling the case study of colonies growth through an activation/inhibition dynamics. Copyright

Simulation of single-electron tunneling circuits

We investigate the use of nanoelectronic structures in cellular non-linear network (CNN) architectures, for potential application in future high density and low power CMOS-nanodevice hybrid circuits. We first review the operation of the single-electron tunneling (SET) transistor to be used in analog processing arrays for image processing applications. We then discuss simple CNN linear architectures using a SET inverter topology as the basis for the non-linear transfer characteristics for individual cells. The basic SET-CNN cell acts as a summing node that is capacitively coupled to the inputs and outputs of nearest neighbor cells. Monte Carlo simulation results are then used to show CNN-like behavior in attempting to realize different functionality such as shadowing. Finally, we discuss the speed and signal delay in SET networks, and estimate the power consumption of the SET-CNN and compare it to a state-of-the-art CMOS processor.

High-speed and low-power cellular non-linear networks using single-electron tunneling technology

We investigate the use of nanoelectronic structures in cellular non-linear networks (CNN) for potential applications in future high-density and low-power CMOS-nano device hybrid circuits. We first discuss simple CNN linear architectures using single-electron tunneling (SET) transistor summing-inverter circuits, which are capacitively coupled to the inputs and outputs of nearest neighbor cells. Monte Carlo simulation results are then used to show CNN-like behavior in realizing different functionality such as shadowing. The SET-CNN circuit was optimized to operate at 1 GHz, which is a desirable feature for high-speed image processing applications. Finally, we estimate the power consumption of the SET-CNN and compare it to a state-of-the-art CMOS processor.

Single-electron charging effects in Si MOS devices

Abstract Single-electron charging of small quantum dot structures has been observed for many years. Only recently, however, have the effects been observed in Si device structures suitable for integration into other Si technologies. In this talk, the background of work in Si will be reviewed and its applications to unique device and circuit architectures will be discussed. Experimental results obtained using double-gated quantum dots embedded within a Si MOSFET will be discussed. While the present results are primarily at low temperature, they promise the application of single-electron technology to more integrated circuitry.