Costas J. Spanos

Modeling within-die spatial correlation effects for process-design co-optimization

Within-die spatial correlation of device parameter values caused by manufacturing variations has a significant impact on circuit performance. Based on experimental and simulation results, we: (1) characterize the spatial correlation of gate length over a full-field range of horizontal and vertical separation; (2) develop a rudimentary spatial correlation model; and (3) investigate its impact an the variability of circuit performance.

Specular spectroscopic scatterometry

Scatterometry is one of the few metrology candidates that has true in situ/in-line potential for deep submicrometer critical dimension (CD) and profile analysis. Most existing scatterometers are designed to measure multiple incident angles at a single wavelength on periodic gratings. We extend this idea by deploying specular spectroscopic scatterometry. Specular spectroscopic scatterometry (SS) is designed to measure the zeroth-order diffraction response at a fixed angle of incidence and multiple wavelengths. This mechanism allows the use of existing thin-film metrology equipment, such as spectroscopic ellipsometers, to accurately extract topographic profile information from one-dimensional (1-D) periodic structures. In this work, we developed the grating tool-kit (gtk), which implements several variants of rigorous coupled-wave analysis (RCWA) to accurately and efficiently simulate diffraction behavior of 1-D gratings. Theoretical simulations using this package show that specular spectroscopic scatterometry can be applied in the current semiconductor manufacturing technology, and can be easily extended to the 0.07-/spl mu/m generation. We have also applied a library-based profile extraction methodology to resist and poly focus-exposure matrices patterned using 0.25and 0.18-/spl mu/m lithography and etch technology, respectively, to extract their cross-sectional profiles. Discrepancies between CD-SEM, CD-AFM, and SSS measurements are discussed and explained.

Statistical experimental design in plasma etch modeling

The objective of this work is to obtain a comprehensive set of empirical models for plasma etch rates, uniformity, selectivity, and anisotropy. These models accurately represent the behavior of a specific piece of equipment under a wide range of etch recipes, thus making them ideal for manufacturing and diagnostic purposes. The response characteristics of a CCl/sub 4/-based plasma process used to etch doped polysilicon were examined via a 2/sup 6-1/ fractional factorial experiment followed by a Box-Wilson design. The effects of variation in RF power, pressure, electrode spacing, CCl/sub 4/ flow, He flow and O/sub 2/ flow on several output variables, including etch rate, selectivity, and process uniformity, were investigated. Etch anisotropy was also measured by scanning electron microscopy analysis on a 2/sup 6-2/ fraction of the original experiment. The screening factorial experiment was designed to isolate the most significant input parameters. Using this information as a platform from which to proceed, the subsequent phase of the experiment allowed the development of empirical models of etch behavior using response surface methodology (G. E. P. Box and N. D. Draper, 1987). The models were subsequently used to optimize the etch process. >

Statistical equipment modeling for VLSI manufacturing: an application for LPCVD

An equipment characterization and modeling methodology has been developed. The methodology is based on the development of generic first-principle process models. These models are subsequently refined and fitted to specific manufacturing equipment by using a multistage D-optimal experimental design. The methodology has been successfully applied to a low-pressure chemical vapor deposition (LPCVD) furnace for undoped polysilicon deposition. A two-stage D-optimal experiment with 24 runs has yielded fitted models for the film growth rate and film residual stress. The calibrated models agree well with the experimental data and account for the observed variations. >

Real-time statistical process control using tool data (semiconductor manufacturing)

A process monitoring scheme that takes advantage of real-time information in order to generate malfunction alarms is described. This is accomplished with the application of time-series filtering and multivariate statistical process control. This scheme is capable of generating alarms on a true real-time basis, while the wafer is still in the processing chamber. Several examples are presented with tool data collected from the SECSII port of single-wafer plasma etchers. >

Distributed Energy Consumption Control via Real-Time Pricing Feedback in Smart Grid

This brief proposes a pricing-based energy control strategy to remove the peak load for smart grid. According to the price, energy consumers control their energy consumption to make a tradeoff between the electricity cost and the load curtailment cost. The consumers are interactive with each other because of pricing based on the total load. We formulate the interactions among the consumers into a noncooperative game and give a sufficient condition to ensure a unique equilibrium in the game. We develop a distributed energy control algorithm and provide a sufficient convergence condition of the algorithm. The energy control algorithm starts at the beginning of each time slot, e.g., 15 min. Finally, the energy control strategy is applied to control the energy consumption of the consumers with heating ventilation air conditioning systems. The numerical results show that the energy control strategy is effective in removing the peak load and matching supply with demand, and the energy control algorithm can converge to the equilibrium.

Measurement and Analysis of Variability in 45 nm Strained-Si CMOS Technology

A test-chip in a low-power 45 nm technology, featuring uniaxial strained-Si, has been built to study variability in CMOS circuits. Systematic layout-induced variation, die-to-die (D2D), wafer-to-wafer (W2W) and within-die (WID) variability has been measured over multiple wafers, analyzed and attributed to likely causes in the manufacturing process. Delay is characterized using an array of ring oscillators and transistor leakage current is measured with an on-chip ADC. The key results link systematic layout-dependent and die-to-die variability as being caused by gate patterning and material strain. In comparison to a previous 90 nm experiment, gate proximity now contributes less to frequency variability, causing a 2% change in overall performance, while strain has increased its contribution to about 5% of the overall performance.

Semiconductor yield improvement: results and best practices

The results of a world-wide study on yield improvement are presented. Die yields collected from 21 fabs are transformed via a logit formula and compared. The die yields and die yield improvement rates of the fabs are compared, and manufacturing yield improvement practices are evaluated. Preliminary results of this continuing study indicate that die yield improvement is a function of computer-aided manufacturing practices and statistical process control practices in addition to commonly cited practices such as particle control and advanced manufacturing technology. >

A control system for photolithographic sequences

The goal of our control system is to improve the reliability, accuracy, and economy of operation of a sequence of interrelated processes. We achieve this task by using well known, rigorous statistical techniques to continuously monitor process parameters, detect out-of-control equipment, and then optimally adjust relevant machine inputs to bring the process back on target We have implemented the supervisory control system on the photolithography sequence in the Berkeley Microfabrication Laboratory, where it has been conclusively proven that the supervisory control system increases significantly the capability of the entire process. The supervisory control algorithms, consisting of feedback and feed-forward control, multivariate, model-based statistical process control (SPC), and automated specification management algorithms, are independent of machine and/or process, and can be applied to any semiconductor manufacturing sequence.

Gate Line Edge Roughness Model for Estimation of FinFET Performance Variability

We present a model for estimating the impact of gate line edge roughness (LER) on the performance of double-gate (DG) FinFET devices. Thirteen-nanometer-gate-length DG FinFETs are investigated using a framework that links device performance to commonly used LER descriptors, namely, correlation length (xi), rms amplitude or standard deviation (sigma) of the line edge from its mean value, and roughness exponent ( alpha). Our approach provides physical insight into how LER impacts FinFET performance. In addition, our modeling approach is more efficient than Monte Carlo TCAD simulations and provides comparable results with appropriately selected input parameters. The FinFET device architecture is found to be robust to gate LER effects. Furthermore, a spacer-defined gate electrode (versus a resist-defined gate electrode) provides for reduced variability in performance, indicating that the gate length mismatch has more impact than lateral offset between the front and the back gates.