Craig R. Winterhalter

The effect of circuit parasitic impedance on the performance of IGBTs in voltage source inverters

In order to reduce power losses and increase system power density, IGBT switching speeds in industrial motor drives continue to increase. These fast switching speeds, combined with high switching frequencies, have increased the interaction between the IGBT and the parasitic circuit impedance. This paper describes the switching behavior of fast switching IGBTs in the presence of parasitic circuit impedance. The sources of the parasitic impedance are identified and include the IGBT chip, power device packaging, physical circuit layout and motor load. The interaction between the power devices and circuit parasitic capacitance is shown to cause output voltage distortion that affects the volt-seconds applied to the motor. Analysis of the current paths and voltage distortion levels is performed as a function of the inverter switching state to predict the IGBT switching behavior. It is also found that parasitic capacitance contributes to an increase in the IGBT power loss and a change in the power loss distribution between the IGBT and diode in a power module.

Investigation of common mode current related dc-bus overvoltage in multiple converter systems

Active front end (AFE) converters have been extensively used in industrial motor-drive systems due to their energy regenerative capability and low harmonic distortions. However, the Pulse Width Modulation (PWM) switching operation in AFE converters generates higher common-mode voltage than their non-regenerative diode front-end (DFE) counterparts. Such significant common-mode voltage can be converted to common-mode current through common-mode capacitance in the system. This large common-mode current can cause overvoltage of the dc-bus of a DFE converter system where both AFE and DFE converter systems share the same ac source. This paper investigates such overvoltage phenomena occurring in a DFE dc-bus in a multiple converter system. Mechanism of such dc-bus overvoltage will be explained, and both simulation as well as experimental results are presented to confirm the theoretical analysis. Moreover, a dc-bus clamping circuit is recommended to clamp the DFE dc-bus voltage, thus any overvoltage that could trip the DFE drive can be avoided.

Novel double clamp methodology to reduce shielded cable radiated emissions initiated by electronic device switching

A new “Double Clamp Methodology” (DCM) is proposed that can suppress a cables peak radiated emission in a band centered around noise frequency (fnoise pk) that is generated by Common-Mode (CM) electrical noise current flowing in any product containing pulsed switching devices connected to a shielded cable. DCM is a cable grounding technique that clamps or terminates a shielded cable in two places. The first shield clamp at the switching device output uses traditional well-known cable termination techniques eg. 360° low inductance shield connection to ground. A second shield clamp can be placed at a predetermined cable length from the first, where the cable resonant frequency is known to have ultra-low CM impedance at noise frequency fnoise pk. The cable loop between shield clamp terminations sets up a resonant low impedance at fnoise pk that diverts CM current to the ground plane inside the product, so CM current entering a shielded cable is reduced as well as radiated electric field emissions. Analytical and measurement techniques are provided to determine the correct cable clamp length. Experimental test results confirm DCM effectively controls CM noise current and resulting peak radiated emissions by 12 dBμV/m (~4x), without external suppression components added.

The influence of the DC link inductor design on the rectifier voltage stress in an adjustable speed drive during a mains voltage surge

The use of diode bridge rectifiers in modern adjustable speed drives (ASD) is widespread due to their simplicity and low cost. The diode bridge rectifier is commonly used in conjunction with a passive L-C filter to provide a suitable DC link. The design of the L-C filter involves many factors including its impact on the ASD performance during a mains voltage surge. This paper presents an analytical method to determine the impact of the DC link inductor design on the diode bridge rectifier voltage stress during a mains voltage surge. Several common DC link inductor designs are considered and their effect on the diode bridge rectifier peak voltage stress is shown to be a function of the mutual inductance and also the loading condition of the ASD. Experimental results are obtained that confirm both the analytical and computer simulation models.