Creve Maples

The Design of MIDAS - A Modular Interactive Data Analysis System

A specialized computer facility, designed to provide a highly interactive, graphics-oriented, multi-user environment for the high-speed reduction and analysis of experimental data, is currently Under construction at Lawrence Berkeley Laboratory. The major difficulties in achieving high-speed data analysis (CPU limitations and I/O band-width restrictions) are minimized with MIDAS by using multiple CPUs to parallel-process the data and by utilizing multiple I/O busses with intelligent controllers to permit parallel, asynchronous data transmission to external memory blocks, which then may be switched dynamically to any processor. For data reduction, MIDAS should provide a processing power of about one CDC 7600 per user. Software utilization of the parallel architecture will be relatively transparent to the user, with analysis codes written in Fortran. Prototype tests of this facility are scheduled for summer, 1981.

The Utilization of Parallel Processors in a Data Analysis Environment

The problem of reduction and analysis of experimental data is ideally suited to the utilization of a parallel processing environment. In contrast to an array processor, where the operations are paralleled, the structure of event-mode data, as independent information packets, permits the analysis of each data packet to be carried out by a processor operating asynchronously but in parallel with other processing units. In the MIDAS project a multi-processor array (MPA) consisting of 8 high-level CPUs (with floating point hardware) for calculation, 2 pipelined processors for handling data I/O, and a specialized processor to perform high-speed Boolean operations, is available to each user during analysis. In addition, there are mid-range CPUs to control and monitor each MPA and specialized CPUs to control large mass storage devices.

Utilizing a Multiprocessor Architecture - The Performance of MIDAS

The MIDAS architecture organizes multiple CPUs into clusters called distributed subsystems. Each subsystem consists of an array of processors controlled by a supervisory CPU. The multiprocessor array is composed of commercial CPUs (with floating point hardware) and specialized processing elements. Interprocessor communication within the array may occur either through switched memory modules or common shared memory. The architecture permits multiple processors to be focused on single problems. A distributed subsystem has been constructed and tested. It currently consists of a supervisor CPU; 16 blocks of independently switchable memory; 9 general purpose, VAX-class CPUs; and 2 specialized pipelined processors to handle I/O. Results on a variety of problems indicate that the subsystem performs 8 to 15 times faster than a standard computer with an identical CPU. The difference in performance represents the effect of differing CPU and I/O requirements.

Using Multiprocessor Systems in Scientific Applications

The MIDAS multiprocessor system is a multi-level, hierarchial structure developed at the Advanced Computer Architecture Laboratory of the University of Californias Lawrence Berkeley Laboratory. A two-stage, 11-processor system has been operational for about 18 months. It has been employed to investigate techniques for decomposing a variety of problems and algorithms into a parallel processor environment. The performance results for a number of different applications will be discussed. These include scientific data analysis, Monte Carlo calculations, solutions to partial differential calculations (using finite-difference methods), and problems in accelerator design. Language extensions and programming techniques for the data-flow architecture will also be presented.

An Interactive Parallel Processor for Data Analysis

A parallel array of eight minicomputers has been assembled in an attempt to deal with kiloparameter data events. By exporting computer system functions to a separate processor, we have been able to achieve computer amplification linearly proportional to the number of executing processors.