Cristiano Santos

Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs

DRAM cells use capacitors as volatile and leaky bit storage elements. The time spent without refreshing them is called retention time. It is well known that the retention time depends inverse exponentially on the temperature. In 3D stacking, the challenges of high power densities and thermal dissipation are exacerbated and have a much stronger impact on the retention time of 3D-stacked WIDE I/O DRAMs that are placed on top of an MPSoC. Consequently, it is very important to study the temperature behaviour of WIDE I/O DRAMs. To the best of our knowledge, no investigations based on real measurements were done for stacked DRAM-on-logic devices. In this paper, we first provide detailed measurements on temperature-dependent retention time and bit error rates of WIDE I/O DRAMs. To obtain the correct temperature distribution of the WIDE-I/O DRAM die we use an advanced thermal modelling tool: the DOCEA AceThermalModelerTM (ATM). The WIDE I/O DRAM retention times and bit error rates are compared to the behaviour of 2D-DRAM chips (DIMMs) with the help of an advanced FPGA-based test system. We observed data pattern dependencies and variable retention times (VRTs). Second, based on this data, we develop and validate a SystemC-TLM2.0 DRAM bit error rate model. Our proposed DRAM bit error model enables early investigations on the temperature vs. retention time trade-off in future 3D-stacked MPSoCs with WIDE I/O DRAMs in SystemC-TLM2.0 environments.

8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links

By shortening communication distance across dies, 3D technologies are a key to continued improvements in computing density. For 4G telecom baseband processing, specific computing units arranged in a regular network-on-chip (NoC) array provide power-efficient computation [1]. However, for advanced MIMO processing, more computing power is required when the number of antennas increases. This paper presents a homogeneous 3D circuit composed of regular tiles assembled using a 4x4x2 network-on-chip, using robust and fault tolerant asynchronous 3D links, providing 326MFlit/s @ 0.66pJ/b, fabricated in CMOS 65nm technology using 1980 TSVs in a Face2Back configuration.

A transistor sizing method applied to an automatic layout generation tool

This paper presents a method of transistor sizing, integrated to a row-based automatic layout generation tool. Automatic layout generation is able to generate a more optimized layout in relation to the standard cell approach because standard cell libraries present a limited number of cells. Most transistor sizing algorithms propose continuous sizing according to the performance constraints and hence cannot be applied in row-based layouts. In this paper, transistors are folded to keep the row height, discretely sizing the transistor. In order to save the final area of the circuit, only transistors in the longest sensitizable paths are sized. The efficiency of the algorithm is measured in relation to area and delay.

System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuit

Considering the effects of thinned silicon dies and structures like TSVs and μ-bumps is essential for accurate thermal analysis of vertically integrated circuits. This paper presents an innovative compact thermal modeling approach for 3D ICs targeting system-level thermal analysis. This method uses material homogenization and formal reduction techniques for model simplification. It enables taking into account the microscopic structures required for 3D integration while keeping the model complexity affordable for fast simulations. A complete system including a packaged 65nm memory-on-logic circuit, socket and board has been modeled using the proposed thermal modeling approach. Power dissipation hot spots are emulated in the 3D circuit by using a set of resistive heaters while temperature is monitored using integrated thermal sensors. Simulation results from both steady-state and transient analyses show the thermal model is able to capture the hot spot effects with fast simulation times. Thermal data extracted from the 3D circuit demonstrate that simulation fits the thermal transient response and that steady-state analysis for various power profiles presents a worst case temperature error lower than 12% and an average error of 4.2%.

Thermal performance of 3D ICs: Analysis and alternatives

3D ICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology. This work brings an overview of the thermal impact of the 3D integration technology, providing means to investigate causes and alternative solution for the existing thermal issues in 3D ICs. A complete chip-package-board system is used to evaluate the thermal performance of a memory-on-logic 3D circuit. Thermal simulations and silicon measurements from two fabricated versions of a SoC instrumented with integrated heaters and thermal sensors are compared to reveal the temperature profile changes resulting from 3D integration. This work also provides a comprehensive discussion of the four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs. This study demonstrates, for instance, that non-thinned stacked dies may act as heat spreaders and help to alleviate hotspot issues while TSVs are in fact not effective for thermal mitigation. Lastly, this work proposes the use of graphite-based heat spreaders as an alternative to compensate the poor heat dissipation properties exhibited in 3D ICs. Simulation results show a temperature reduction of up to 45μC and suggest this is a potential cost-effective method for thermal management. The discussion presented in this work aims to understand the thermal impact of technology parameters inherent in 3D integration and supports system architects and designers to take early design decisions and prevent thermal issues.

A produção científica de enfermagem acerca da clínica: uma revisão integrativa

The objective of this study was to learn about the production of nursing knowledge in Brazil associated with the clinic theme. This is a qualitative study performed by means of an integrative review. Data collection was performed on the SciELO database using the keywords nursing and clinic, present in the abstracts of articles. It was found that the clinic is seen as an instrument used to establish connections between research and nursing care, having a constant movement of constructing and deconstructing knowledge and practices. The study results may contribute with the production of research and knowledge in nursing, providing elements to subsidize improvements in nursing care, in which there is an interaction between practice and biological and non-biological knowledge.The objective of this study was to learn about the production of nursing knowledge in Brazil associated with the clinic theme. This is a qualitative study performed by means of an integrative review. Data collection was performed on the SciELO database using the keywords nursing and clinic, present in the abstracts of articles. It was found that the clinic is seen as an instrument used to establish connections between research and nursing care, having a constant movement of constructing and deconstructing knowledge and practices. The study results may contribute with the production of research and knowledge in nursing, providing elements to subsidize improvements in nursing care, in which there is an interaction between practice and biological and non-biological knowledge.

A FAMÍLIA NA UNIDADE DE PEDIATRIA: PERCEPÇÕES DA EQUIPE DE ENFERMAGEM ACERCA DA DIMENSÃO CUIDADORA

The goal of this study was to identify the meaning of care to the hospitalised child’s family for the nursing team of the paediatrics unit of an academic hospital in southern Brazil. Five nurses, three nursing technicians ISSN 0717-2079 CIENCIA Y ENfERMERIA XVII (2): 87-95, 2011 * Enfermeira, Doutoranda do Programa de Pós-graduação em Enfermagem da Universidade Federal do Rio Grande – FURG, membro do Grupo de Estudos e Pesquisas em Enfermagem e Saúde da Criança e do Adolescente GEPESCA/FURG, Bolsista FURG. Rio Grande, Brasil, e-mail: lenice_ds@yahoo.com.br, Endereço: Av. Itália, 2111, Bloco 18A, ap. 103, CEP:96203-000. ** Enfermeira. Doutora, professora do Departamento de Enfermagem da FURG. Diretora adjunta do hospital Universitário Dr. Miguel Riet Corrêa Jr., Líder do GEPESCA/FURG, Rio Grande, Brasil, e-mail: acgomes@mikrus.com.br *** Enfermeira. Doutora, professora do Departamento de Enfermagem da FURG. Líder do Grupo de Estudo e Pesquisa de Família, Enfermagem e Saúde (GEPEFES). Coordenadora do Programa de Pós-graduação em Enfermagem da Universidade Federal do Rio Grande, Rio Grande, Brasil, e-mail: marare@brturbo.com.br **** Enfermeiro pela FURG. Membro do GEPESCA/FURG, Rio Grande, Brasil, e-mail: cristianoschroder@yahoo.com.br ***** Enfermeira. Mestre em Enfermagem pela FURG. Doutoranda do Programa de Pós-Graduação da FURG. Integrante do Grupo de Estudo e Pesquisa em Gerontogeriatria, Enfermagem/Saúde e Educação (GEP-GERON). Bolsista da CAPES. Rio Grande, Brasil, e-mail: babi@vetorial.netEl objetivo del estudio fue identificar el significado del cuidado a la familia de ninos hospitalizados para el equipo de enfermeria de la unidad pediatrica de un hospital universitario en el sur de Brasil. Los participantes de la investigacion fueron: cinco enfermeras, tres tecnicas en enfermeria y dos auxiliares de enfermeria. Fueron seguidos todos los preceptos eticos que rigen las investigaciones con seres humanos. Los datos fueron recolectados en noviembre de 2006 a traves de entrevista semiestructurada y analizados segun el metodo hermeneutico-dialectico. Los resultados muestran que los profesionales reconocen que la familia tiene necesidades, siendo parte inseparable de la asistencia. Aunque fue posible verificar que a pesar de haber una fuerte tendencia a valorar los aspectos tecnicos y mecanicos de la asistencia representados por los cuidados directos, el equipo de enfermeria realiza una serie de cuidados indirectos dirigidos a un abordaje global y humanizado. Se concluye que es necesario que el equipo de enfermeria que presta asistencia a ninos hospitalizados emprenda con dinamismo su atencion para cubrir las necesidades de sus familiares, apartandose asi de un modelo tecnico y mecanico, valorando su hacer, volviendose mas visible y humanizado.

Using TSVs for thermal mitigation in 3D circuits: Wish and truth

3D technology is envisioned to offer advanced integration capabilities, enabling heterogeneous system integration and offering improved performance and reduced power consumption thanks the so-called Through Silicon Vias (TSVs). Nevertheless, 3D integration is facing strong thermal issues due to its higher power density and reduced heat dissipation properties. In previous studies, it has been often reported the use of TSV insertion techniques for thermal mitigation in 3D stacked circuits. However, due to the thin oxide layer isolating TSVs from silicon substrate, the expected thermal mitigation is actually not effective for the current TSV technologies. This paper firstly provides an analytical study to project the potential benefits and drawbacks of using TSVs for thermal mitigation. Detailed FEM simulations and experimental silicon data from a dedicated thermal test chip are then used to confirm the projections and demonstrate that TSVs may even increase the temperature of hotspots. This paper secondly reports the study of the thermal performance of multiple TSV arrays using thermal simulations for various system-level configurations, including a WideIO compatible 3D circuit. Similar results are obtained where, besides not alleviating thermal issues, TSVs may produce exacerbated hotspots. The results presented in this paper indicate that the use of additional area costly TSVs for thermal mitigation is not worthy.

A New Transistor-Level Layout Generation Strategy for Static CMOS Circuits

A new transistor-level layout generation strategy is presented in this paper. This strategy makes possible to design static CMOS cells for any logic function on demand, allowing a logic minimization without any logic constraints. Results show that this new full automatic transistor-level layout generation methodology is very promising. Thus, the strategy aims at reducing the number of transistors targeting less static consumption and performing transistor sizing to improve circuit performance.

Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits

This article describes heat dissipation challenges in 3-D ICs; using two case studies, it also presents insights and design guidelines for 3-D thermal management.