Cui Gang

Redundant Multithreading Architecture Overview

To overcome the ever-increasing susceptibility to transient-fault in processors, various redundant multithreading (RMT) architectures have been proposed, which is becoming a most effective approach for detecting and recovering from transient-fault. This paper surveys a wide range of RMT architectures—from the original AR-SMT(A-stream R-stream Simultaneous MultiThreading) to the most-recent SD-SRT (Slack-Decode Simultaneous Redundant Threading), presenting traverse analyses and comparisons among them, and hereby demonstrates its evolution and tendency. Finally, some directions and suggestions are put forward for the further RMT research and development.

TRSTR: A Fault.Tolerant Microprocessor Architecture Based on SMT

Based on Simultaneous Multithreading (SMT), we propose a fault-tolerant scheme called Tri-modular Redundantly and Simultaneously Threaded processor with Recovery (TRSTR). TRSTR features as following: First, we introduce an arbitrator context into the conventional SRT (Simultaneous and Redundantly Threaded), which acts as an arbitrator when results from the other two contexts disagree, or acts as an ordinary thread generally, thus making full use of SMTs parallelism. Second, we append reconfigurable feature to sphere of replication in SRT, making it more flexible for changing demands and situations. Third, TRSTR has two working modes: Tri-Simultaneous with Voting (TSV) and Dual-Simultaneous with Arbitrator (DSA), which can switch at will. Finally, in addition to transient-fault coverage, TRSTR has on-line self-checking and self-recovering abilities, so as to shield off some permanent faults and reconfigure itself without stopping the crucial job, improving its reliability and availability.