Cuneyt F. Bazlamacci

Array Design for Trie-based IP Lookup

A novel SRAM based multi-pipeline array design is proposed for trie-based IP lookup. The new structure increases parallelism and achieves a higher throughput, making for example a 2 Tbps IP lookup speed possible. The new design is scalable and applicable to IPv6.

Effect of Application Mapping on Network-on-Chip Performance

Network-on-Chip (NoC) is a developing and promising on-chip communication paradigm that improves scalability and performance of System-on-Chips. NoC design flow contains many problems from different areas, for example networking, embedded design and computer architecture. Application mapping is one of these problems, which is well studied in literature but generally considered as a communication energy minimization problem. The present study discusses the effect of application mapping on network parameters such as average queuing delay or packet loss rates of routers. On the other hand, self similarity is a phenomenon that is used to characterize Ethernet and/or wide area network traffic, as well as most of on-chip network traffic. The main concern of this study is to analyze the effect of application mapping on network related parameters by using an on-chip traffic characterization that contains self similarity. The results of our computational study show that mapping of cores may have a significant degenerative effect on network performance, and so adding network related terms to application mapping problem may improve the overall on-chip network performance considerably.

Energy and buffer aware application mapping for networks-on-chip with self similar traffic

Networks-on-chip (NoC) is a promising on-chip communication paradigm that improves scalability and performance of System-on-Chips. NoC design flow contains many problems from different areas, such as networking, embedded design and computer architecture. Application mapping is one of these problems, which is generally considered in the form of a communication energy minimization problem. Self similarity is a traffic model that is used to characterize Ethernet and/or wide area network traffic, as well as on-chip network traffic. The present paper tackles the application mapping problem from a networking point of view using self similar traffic assumption and aims to find a mapping solution that improves network performance in terms of buffer utilization while simultaneously minimizing the total communication energy consumption. In this study, by using a self similar on-chip traffic characterization, an application mapping problem definition, which contains both energy and buffer utilization concerns is proposed. In order to solve this intractable problem, a genetic algorithm based solution is derived and implemented. Execution of the algorithm on different test cases has proven that such a mapping formulation avoids high buffer over utilizations while keeping the communication energy requirement still low.

A reconfigurable computing platform for real time embedded applications

Reconfigurable computing is a promising technique for real time computing-intensive embedded applications. In this paper, we propose a novel hardware task model and an optimal 2D surface partitioning strategy for managing a partially run time reconfigurable hardware resource. A mesh network-on-chip is designed to be used as the communication environment for the hardware tasks. An offline design flow is proposed for generating the bit-stream and finally, an online real time operating system scheduler that supports true hardware multitasking is presented. The proposed components form the necessary building blocks of a complete reconfigurable computing platform suitable for real time computing-intensive embedded applications.

A Distributed Heuristic Algorithm for the Rectilinear Steiner Minimal Tree Problem

Rectilinear Steiner minimal tree (RSMT) problem finds a minimum length tree that interconnects a given set of points by only horizontal and vertical line segments and by using extra points if necessary. In this paper, to speedup the RSMT construction, two recently developed successful heuristic algorithms, namely rectilinear steiner tree (RST) by Zhou and batched greedy algorithm (BGA) by Kahng , have been used as the basis. Following a slight modification on RST, which led to a nonrecursive and a considerably faster version, a partially parallelized and distributed form of this modified algorithm is proposed. Computational tests using large random data sets have shown the advantage of the modification on RST, and tests conducted on a cluster of workstations have proven the proposed distributed approach to be very promising particularly for large problem instances.

Evaluation of energy and buffer aware application mapping for networks-on-chip

Abstract Networks-on-Chip (NoC) is a communication paradigm for Systems-on-Chip (SoC). NoC design flow contains many problems, one of which is called as application mapping problem, which is generally solved in the literature by considering minimization of the communication energy consumption only. Energy and Buffer Aware Application Mapping (EBAM) is a recently proposed method, which handles the application mapping issue as a joint optimization problem for minimizing the energy consumption and buffer utilization simultaneously. EBAM avoids possible high input loads on router buffers at the early mapping stage by using a priori traffic characteristics of the application. Self similarity is already an accepted model in local and wide area networks and many on-chip applications have also been proven to have self similar characteristics. EBAM therefore employs self similar traffic in its joint optimization process and a genetic algorithm is already proposed for its solution. This paper presents a simulation study that evaluates EBAM in terms of network parameters such as buffer utilization and end-to-end delay. For this, a self-similar traffic generator module is implemented first on a well known NoC simulator and then buffer utilization of routers and end-to-end delay under self similar traffic are observed. Simulation results show that the method enhances buffer utilization and end-to-end delay against a reasonable energy trade off. A routing protocol selection task follows the mapping stage in a typical NoC design flow hence our paper also presents a computational study that evaluates the effect of EBAM use on commonly encountered on-chip routing algorithms. Results reveal that simple XY routing protocol, compared to others, performs better on mappings obtained by EBAM, which indicates that the need for complicated routing protocols may be eliminated.

Minimum concave cost multicommodity network design

The minimum concave cost multicommodity network design problem (MCMNDP) arises in many application areas, such as transportation planning, energy distribution systems and especially in the design of both packet and circuit switching backbone networks. Exact concave cost optimization algorithms have been developed but they are applicable only if the network size is small. Therefore, MCMNDP is usually solved using non-exact iterative methods. In this paper, such heuristic techniques proposed within the context of circuit switching and packet switching network design are evaluated in detail. Following a comprehensive literature survey, Yaged’s linearization, Minoux’s greedy and Minoux’s accelerated greedy methods have been selected for the circuit switching network design case for further investigation. Minoux’s greedy methods are found to create routes that include cycles causing degradation in the quality of the solution; therefore, we propose a simple but effective modification scheme as a cycle elimination strategy. Similarly, but within the context of packet switching network design, Gerla and Kleinrock’s concave branch elimination, Gersht’s greedy, and Stacey’s concave link elimination methods have been selected for further investigation. All of these methods consider aggregate flows on each link, simultaneously re-routing more than one commodity in one step. In this paper, we propose an alternative disaggregate approach, where only one commodity is handled at a time. Our final proposal is the adaptation of the algorithms proposed for circuit switching network design to the packet switching case. Then an extensive comparative computational study is performed for a number of networks and cost structures to help establish the best method with respect to time and solution quality. Our computational results have shown that the performances of the MCMNDP algorithms heavily depend on the network type and the cost structure. The results have also revealed that our proposed modification to Minoux greedy to eliminate cycles leads to considerable improvements and our proposed disaggregate approach gives the best result in some networks with certain cost structures.

One-Way Active Delay Measurement With Error Bounds

This paper deals with the problem of measuring the delay of a packet in a network with an associated error bound, but without having a need for clock synchronization and for any form of bidirectional messaging between the sender and receiver. A novel lightweight technique is proposed that aims at keeping the actual error made in the delay estimation very low while simultaneously providing a good error bound for each individual estimated packet delay. One-way delay measurement without clock synchronization and messaging cannot guarantee an error bound on delay estimations in general; however, we show that this is possible using periodic probe packets and appropriate assumptions that are compliant with the physical conditions of the environments within which the sender and receiver operate. Although we calculate an error bound for all our delay estimates, the main purpose is to have a much smaller actual error in these delay estimates in comparison with the computed error bound and other methods existing in the literature. The proposed method is evaluated against a recently reported technique of the same category and is shown to be much more superior overall.

HyFI: Hybrid flow initiation in software defined networks

Software defined networking (SDN) provides techniques to facilitate the management of computer networks in a centralized and integrated architecture by separating the control plane from the data plane in packet forwarding devices and middleboxes. By creating this abstraction layer, SDN allows control of network middleboxes remotely from a controller point, which is either connected directly (out-of-band control using dedicated links) or indirectly (in-band control using the available data network links) to the middleboxes. Flow initiation methods used for unknown flows in out-of-band control mechanism are not optimized for use in in-band controllers. Therefore, handling flow initiation and controller discovery for hybrid SDNs and cases where the control and data traffic flow on the same network are still challenges yet to be addressed. The present study first includes a review of the current state-of-the-art in tackling flow initiation challenge and then addresses the problem in SDNs with in-band controllers by proposing a hybrid mechanism that aims to minimize the delay in the transmission of new flows during flow initiation. Our proposal uses a unified network map on the controller to form apriori network information and then configures the switches appropriately. By modeling flow initiation in OpenFlow, the present study also compares the implications of the proposal with the flow initiation methods currently used in out-of-band controllers today.

Hybrid Data Structure for IP Lookup in Virtual Routers Using FPGAs

Virtualization allows heterogeneous networks to share same underlying physical substrate. A single router fulfills the roles of multiple virtual routers by maintaining all the forwarding tables. Therefore, multiple virtual routers can run on a single substrate router, and multiple organizations share this single physical router. A single router plays the role of multiple independent virtual routers while providing the necessary isolation and resource management. Hence, a virtual router should fulfill the following requirements:\begin{itemize} \item \emph{Fair resource usage}: Router resources should be fairly shared among the virtual routers. \item \emph{Fault isolation}: A fault occurring in a particular virtual network should not affect the operation of other virtual networks. \item \emph{Security}: Traffic from one virtual network should not be mixed with the traffic from any other virtual network. \end{itemize}Storing these virtual routing tables separately leads to a large memory requirement and poor resource sharing. Therefore, merging emerges to be a desirable solution. Existing merging algorithms use leaf pushing technique and a shared next hop data structure to eliminate the large memory bandwidth requirement. However, the size of the shared next hop table grows linearly with the number of virtual routers. Due to the limited on-chip memory and the number of I/O pins of Field Programmable Gate Arrays (FPGAs), existing designs cannot support large number of virtual routing tables and/or large number of prefixes. We propose a compact trie representation and a hybrid data structure to reduce the memory consumption of a single virtual router. Our data structure achieves substantial memory compression without the need for backtracking. The proposed hybrid data structure is also used to merge different virtual routing tables. The approach does not require leaf-pushing and reduces the size of each entry of the data structure. Our data structure achieves a substantial memory reduction of