Curt Berg

A BiCMOS 50 MHz cache controller for a superscalar microprocessor

A description is given of a BiCMOS 50-MHz, 2.2 M-transistor cache controller (CC) chip which supports up to 2 MB of direct-mapped secondary cache for a superscalar microprocessor chip (PU) and interfaces with two multiprocessor (MP) buses. One is the MBus, a circuit-switched MP system bus operating at TTL (transistor-transistor logic) levels. The other is the XBus, a local packet-switched bus operating at either TTL or Gunning-transceiver logic (GTL) levels. In XBus mode, the CC connects to MP buses through buswatcher chips, up to four of which can be connected to the CC to support 4 MP buses. With XBus interface, the CC can support customized MP buses.<<ETX>>

A second-level cache controller for a super-scalar SPARC processor

The design of a BiCMOS 50-MHz, 2.2-million transistor, second-level cache controller chip (CC) for a SPARC super-scalar CPU (PU) is described. This chip is designed to control up to 2 MB of second-level cache (E

Shared memory management in a switched network element

) so that the effective memory latency is reduced, and to support two different multiprocessor (MP) system buses, the MBus and the Dynabus. CC isolates PU and E

System having multiple arbitrating levels for arbitrating access to a shared memory by network ports operating at different data rates

, which operate with a faster processor clock, from the rest of the system, which may operate with a slower system clock, through multiple FIFOs (first in, first outs) and synchronizers. With the isolation, the PU can access E

Methods and apparatus for improving cache consistency using a single copy of a cache tag memory in multiple processor computer systems

in a pipelined fashion with a peak rate of one double-word (64-bit/DW) every processor cycle for both read and write.<<ETX>>