Cyril Cabral

Tantalum as a diffusion barrier between copper and silicon: Failure mechanism and effect of nitrogen additions

The interaction of Cu with Si separated by thin (50 nm) layers of tantalum, Ta2N, and a nitrogen alloy of Ta has been investigated to determine the factors that affect the success of these materials as diffusion barriers to copper. Intermixing in these films was followed as a function of annealing temperature by in situ resistance measurements, Rutherford backscattering spectra, scanning electron microscopy, and cross‐section transmission electron microscopy. Ta prevents Cu‐silicon interaction up to 550 °C for 30 min in flowing purified He. At higher temperatures, copper penetration results in the formation of η‘‐Cu3Si precipitates at the Ta‐Si interface. Local defect sites appear on the surface of the sample in the early stages of this reaction. The Ta subsequently reacts with the substrate at 650 °C to form a planar hexagonal‐TaSi2 layer. Ta silicide formation, which does not occur until 700 °C in a Ta‐Si binary reaction couple, is accelerated by the presence of Cu. Nitrogen‐alloyed Ta is a very similar...

Towards implementation of a nickel silicide process for CMOS technologies

In this paper, we review some of the advantages and disadvantages of nickel silicide as a material for the electrical contacts to the source, drain and gate of current and future CMOS devices. We first present some of the limitations imposed on the current cobalt silicide process because of the constant scaling, of the introduction of new substrate geometries (i.e. thin silicon on insulator) and of the modifications to the substrate material (i.e. SiGe). We then discuss the advantages of NiSi and for each of the CoSi2 limitations, we point out why Ni is believed to be superior from the point of view of material properties, miscibility of phases and formation mechanisms. Discussion follows on the expected limitations of NiSi and some of the possible solutions to palliate these limitations.

Mechanisms for microstructure evolution in electroplated copper thin films near room temperature

We present a model which accounts for the dramatic evolution in the microstructure of electroplated copper thin films near room temperature. Microstructure evolution occurs during a transient period of hours following deposition, and includes an increase in grain size, changes in preferred crystallographic texture, and decreases in resistivity, hardness, and compressive stress. The model is based on grain boundary energy in the fine-grained as-deposited films providing the underlying energy density which drives abnormal grain growth. As the grain size increases from the as-deposited value of 0.05–0.1 μm up to several microns, the model predicts a decreasing grain boundary contribution to electron scattering which allows the resistivity to decrease by tens of a percent to near-bulk values, as is observed. Concurrently, as the volume of the dilute grain boundary regions decreases, the stress is shown to change in the tensile direction by tens of a mega pascal, consistent with the measured values. The small ...

Ultrathin HfO 2 films grown on Silicon by atomic layer deposition for advanced gate dielectrics applications

We report on growth behavior, structure, thermal stability and electrical properties of ultrathin (<10 nm) hafnium oxide films deposited by atomic layer deposition using sequential exposures of HfCl4 and H2O at 300°C on a bare silicon surface or a thin thermally grown SiO2-based interlayer. Compared to good quality continuous films deposited on SiO2 surfaces, HfO2 deposited on HF-last treated Si surfaces show a non-uniform, island-like morphology and poor electrical properties due to poor nucleation on H-terminated Si. As-deposited films have a significant amorphous component and undergo crystallization to a monoclinic phase above ∼500°C. Crystallization behavior is found to be dependent on film thickness with higher crystallization temperatures for thinner films. HfO2 on an ultrathin SiO2 interlayer shows good electrical properties with gate leakage current reduced by a factor of 103 -104 with respect to conventional SiO2 gate dielectrics which justifies its consideration as a candidate for high-K dielectric for future CMOS devices.

Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation

Metal-gate FinFET and FDSOI devices were fabricated using total gate silicidation. Devices satisfy the following metal-gate technology requirements: ideal mobility, low gate leakage, high transconductance, competitive I/sub on//I/sub off/, and adjustable V/sub t/. Six silicide gate materials are presented, as well as two silicide workfunction engineering methods.

(Ba,Sr)TiO 3 dielectrics for future stacked- capacitor DRAM

Thin films of barium-strontium titanate (Ba,Sr)TiO3 (BSTO) have been investigated for use as a capacitor dielectric for future generations of dynamic random-access memory (DRAM). This paper describes progress made in the preparation of BSTO films by liquid-source metal-organic chemical vapor deposition (LS-MOCVD) and the issues related to integrating films of BSTO into a DRAM capacitor. Films of BSTO deposited on planar Pt electrodes meet the electrical requirements needed for future DRAM. The specific capacitance and charge loss are found to be strongly dependent on the details of the BSTO deposition, the choice of the lower electrode structure, the microstructure of the BSTO, the post-electrode thermal treatments, BSTO dopants, and thin-film stress. Films of BSTO deposited on patterned Pt electrodes with a feature size of 0.2 µm are found to have degraded properties compared to films on large planar structures, but functional bits have been achieved on a DRAM test site at 0.20-µm ground rules. Mechanisms influencing specific capacitance and charge loss of BSTO films are described, as are the requirements for the electrode and barrier materials used in stacked-capacitor structures, with emphasis given to the properties of the Pt/TaSi(N) electrode/barrier system. Major problems requiring additional investigation are outlined.

A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates

Threshold voltage (V_t) of a field effect transistor (FET) is observed to shift with stressing time and this stress induced V _t shift is an important transistor reliability issue. V_t shifts that occur under negative gate bias is referred as NBTI and those that occur under positive bias is referred as PBTI or charge trapping. In this paper, we present a comparative study of NBTI and PBTI for a variety of FETs with different dielectric stacks and gate materials. The study has two parts. In part I, NBTI and PBTI measurements are performed for FUSI NiSi gated FETs with SiO₂ SiO₂/HfO₂ and SiO₂/HfSiO as gate dielectric stacks and the results are compared with those for conventional SiON/poly-Si FETs. The main results are: (i) NBTI for SiO ₂/NiSi and SiO₂/HfO₂/NiSi are same as those conventional SiON/poly-Si FETs; (ii) PBTI significantly increases as the Hf content in the high K layer is increased; and (iii) PBTI is a greater reliability issue than NBTI for HfO₂/NiSi FETs. In part II of the study, NBTI and PBTI measurements are performed for SiO2/HfO2 devices with TiN and Re as gates and the results are compared with those for NiSi gated FETs. The main results are: (i) NBTI for SiO ₂/HfO₂/TiN and SiO₂/HfO₂/Re pFETs are similar with those observed for NiSi gated pFETs; and (ii) PBTI in TiN and Re gated HfO₂ devices is much smaller than those observed for SiO₂/HfO₂/NiSi. In summary for SiO₂/HfO₂ stacks, NBTI is observed to be independent of gate material whereas PBTI is significantly worse for FUSI gated devices. Consequently, HfO₂ FETs with TiN and Re gates exhibit over all superior transistor reliability characteristics in comparison to HfO₂/FUSI FETs

The relationship between deposition conditions, the beta to alpha phase transformation, and stress relaxation in tantalum thin films

We demonstrate that the high temperature polymorphic tantalum phase transition from the tetragonal beta phase to the cubic alpha phase causes a large decrease in the resistance of thin films and a complete stress relaxation in films that were intrinsically compressively stressed. 100 nm beta tantalum thin films with intrinsic stresses of 2.0×1010 dynes/cm2 (tensile) to −2.3×1010 dynes/cm2 (compressive) were deposited onto thermally oxidized (100) silicon wafers by evaporation or dc magnetron sputtering with argon. In situ stress and resistance at temperature were measured at 10 °C/min up to 850 °C in purified helium. Upon heating, the main stress mechanisms were elastic deformation at low temperature, plastic deformation at moderate temperatures and stress relief because of the beta‐to‐alpha phase transition at high temperatures. The temperature ranges over which the elastic and plastic deformation and the beta‐to‐alpha phase transition occurred varied with deposition pressure and substrate biasing. Incom...

Reduction of the C54–TiSi2 phase transformation temperature using refractory metal ion implantation

We report that the ion implantation of a small dose of Mo into a silicon substrate before the deposition of a thin film of Ti lowers the temperature required to form the commercially important low resistivity C54–TiSi2 phase by 100–150 °C. A lesser improvement is obtained with W implantation. In addition, a sharp reduction in the dependence of C54 formation on the geometrical size of the silicided structure is observed. The enhancement in C54 formation observed with the ion implantation of Mo is not explained by ion mixing of the Ti/Si interface or implant‐induced damage. Rather, it is attributed to an enhanced nucleation of C54–TiSi2 out of the precursor high resistance C49–TiSi2 phase.

Diffusion barrier properties of transition metal thin films grown by plasma-enhanced atomic-layer deposition

Ta thin films were grown on Si(001) and polycrystalline Si substrates by plasma-enhanced atomic-layer deposition (PE-ALD) using TaCl5 and atomic hydrogen as precursors. The grown films have resistivity of 150–180 μm cm with a small Cl concentration between 0.5 and 2 at. %. The diffusion barrier properties were investigated using bilayer structures consisting of 200 nm Cu deposited by sputtering on ALD Ta films with various thicknesses. Three in situ analysis techniques consisting of x-ray diffraction, elastic light scattering, and resistance analysis were used to determine the diffusion barrier failure temperature of Ta films. The barriers were annealed at a temperature ramp rate of 3 °C/s from 100 to 1000 °C in forming gas. For this method using x-ray diffraction, the barrier failure temperatures were determined by monitoring the disappearance of the Cu(111) x-ray diffraction peak and appearance of Cu silicide diffraction peaks. At the diffusion barrier failure temperature, elastic light scattering indic...