Cyrus E. Tabery

Considerations in Source-Mask Optimization for Logic Applications

In the low k1 regime, optical lithography can be extended further to its limits by advanced computational lithography technologies such as Source-Mask Optimization (SMO) without applying costly double patterning techniques. By cooptimizing the source and mask together and utilizing new capabilities of the advanced source and mask manufacturing, SMO promises to deliver the desired scaling with reasonable lithography performance. This paper analyzes the important considerations when applying the SMO approach to global source optimization in random logic applications. SMO needs to use realistic and practical cost functions and model the lithography process with accurate process data. Through the concept of source point impact factor (SPIF), this study shows how optimization outputs depend on SMO inputs, such as limiting patterns in the optimization. This paper also discusses the modeling requirements of lithography processes in SMO, and it shows how resist blur affect optimization solutions. Using a logic test case as example, the optimized pixelated source is compared with the non-optimized source and other optimized parametric sources in the verification. These results demonstrate the importance of these considerations during optimization in achieving the best possible SMO results which can be applied successfully to the targeted lithography process.

Optimization of mask shot count using MB-MDP and lithography simulation

In order to maintain manageable process windows, mask shapes at the 20nm technology node and below become so complex that mask write times reach 40 hours or might not be writeable at all since the extrapolated write time reaches 80 hours. The recently introduced Model Based Mask Data Preparation (MB-MDP) technique is able to reduce shot count and therefore mask write time by using overlapping shots. Depending on the amount of shot count reduction the contour of the mask shapes is changed leading to the question how the mask contour influences wafer performance. This paper investigates the tradeoff between mask shot count reduction using MB-MDP and wafer performance using lithography simulation. A typical Source-Mask-Optimization (SMO) result for a 20nm technology will be used as an example.

Evaluation of lithographic benefits of using ILT techniques for 22nm-node

As increasing complexity of design and scaling continue to push lithographic imaging to its k1 limit, lithographers have been developing computational lithography solutions to extend 193nm immersion lithography to the 22nm technology node. In our paper, we investigate the beneficial source or mask solutions with respect to pattern fidelity and process variation (PV) band performances for 1D through pitch patterns, SRAM and Random Logic Standard Cells. The performances of two different computational lithography solutions, idealized un-constrained ILT mask and manhattanized mask rule constrain (MRC) compliant mask, are compared. Additionally performance benefits for process-window aware hybrid assist feature (AF) are gauged against traditional rule-based AF. The results of this study will demonstrate the lithographic performance contribution that can be obtained from these mask optimization techniques in addition to what source optimization can achieve.