D. A. Buchanan

Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's

Quantum-mechanical modeling of electron tunneling current from the quantized inversion layer of ultra-thin-oxide (<40 /spl Aring/) nMOSFETs is presented, together with experimental verification. An accurate determination of the physical oxide thickness is achieved by fitting experimentally measured capacitance-versus-voltage curves to quantum-mechanically simulated capacitance-versus-voltage results. The lifetimes of quasibound states and the direct tunneling current are calculated using a transverse-resonant method. These results are used to project an oxide scaling limit of 20 /spl Aring/ before the chip standby power becomes excessive due to tunneling currents,.

CMOS scaling into the nanometer regime

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFETs, low-temperature CMOS, and double-gate MOSFETs, which may lead to the outermost limits of silicon scaling.

Passivation and depassivation of silicon dangling bonds at the Si/SiO2 interface by atomic hydrogen

Atomic hydrogen is found to simultaneously passivate and depassivate silicon dangling bonds at the Si(111)/SiO2 interface at room temperature via the reactions Pb+H0→PbH and PbH+H0→Pb+H2. The passivation reaction occurs more efficiently keeping the steady‐state Pb density at a low value of only 3–6×1011 cm−2 during atomic hydrogen exposure. This low Pb density can only account for a small fraction of the total number of interface states produced by atomic hydrogen.

Volatile and non-volatile memories in silicon with nano-crystal storage

A single transistor memory structure, with changes in threshold voltage exceeding /spl ap/0.25 V corresponding to single electron storage in individual nano-crystals, operating in the sub-3 V range, and exhibiting long term to non-volatile charge storage is reported. As a consequence of Coulombic effects, operation at 77 K shows a saturation in threshold voltage in a range of gate voltages with steps in the threshold voltage corresponding to single and multiple electron storage. The plateauing of threshold shift, operation at ultra-low power, low voltages, and single element implementation utilizing current sensing makes this an alternative memory at speeds lower than those of DRAMs and higher than those of E/sup 2/PROMs, but with potential for significantly higher density, lower power, and faster read.

Ultrathin high-K gate stacks for advanced CMOS devices

Reviews recent progress in and outlines the issues for high-K high-temperature (/spl sim/1000/spl deg/C) poly-Si CMOS processes and devices and also demonstrate possible solutions. Specifically, we discuss device characteristics such as gate leakage currents, flatband voltage shifts, charge trapping, channel mobility, as well as integration and processing aspects. Results on a variety of high-K candidates including HfO/sub 2/, Al/sub 2/O/sub 3/, HfO/sub 2//Al/sub 2/O/sub 3/, ZrO/sub 2/, silicates, and AlN/sub y/(O/sub x/) deposited on silicon by different deposition techniques are shown to illustrate the complex issues for high-K dielectric integration into current Si technology.

Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides

The electrical characteristics (C-V and I-V) of n+ - and p+ -polysilicon-gated ultrathinoxide capacitors and FETs were studied extensively to determine oxide thickness and to evaluate tunneling current. A quantum-mechanical model was developed to help understand finite inversion layer width, threshold voltage shift, and polysilicon gate depletion effects. It allows a consistent determination of the physical oxide thickness based on an excellent agreement between the measured and modeled C-V curves. With a chip standby power of ≤0.1 W per chip, direct tunneling current can be tolerated down to an oxide thickness of 15-20 A. However, transconductance reduction due to polysilicon depletion and finite inversion layer width effects becomes more severe for thinner oxides. The quantum-mechanical model predicts higher threshold voltage than the classical model, and the difference increases with the electric field strength at the silicon/oxide interface.

Anode hole injection and trapping in silicon dioxide

Hole injection into silicon dioxide films from the polycrystalline‐silicon anode or from the anode/oxide interface is demonstrated to unequivocally occur for any case where electrons are present in the oxide conduction band and where the average electric field in the oxide exceeds 5 MV/cm (thick‐film limit) or the voltage drop across the oxide layer is at least 8 V (thin‐film limit). The hole generation is directly shown to be related to the appearance of hot electrons with kinetic energies greater than 5 eV in the oxide conduction band near the anode region. Monte Carlo simulations confirm that the electron energy distribution at the anode is the controlling variable and that hot hole injection occurs mostly over the anode/oxide energy barrier.

Self‐consistent modeling of accumulation layers and tunneling currents through very thin oxides

Poisson and Schrodinger equations are solved self‐consistently for accumulated layers in metal‐oxide‐semiconductor devices and applied to the calculation of tunneling currents at 300 K and 77 K and extraction of parameters for very thin oxides. Calculations at 300 K show strong agreement with measured tunneling currents and also point out the sources of inaccuracies in extracting thicknesses of oxides by electrical methods such as through measurement of capacitance. Direct tunneling current in thin oxides (1.5–2.0 nm) are shown to achieve larger than 1  A /cm2 current density for applied voltages smaller than 3 V, pointing to possibilities of achieving high endurance injection across thin oxides. Comparison of calculations using a classical approach and self‐consistent approach shows fortuitous agreements in tunneling currents despite large differences in the physical models. Appropriate methods for calculating tunneling currents from bound and extended quantum states are also described.

Interface and bulk trap generation in metal‐oxide‐semiconductor capacitors

The effects of electron‐hole pair recombination near the silicon/silicon dioxide interface of aluminum‐gate metal‐oxide‐semiconductor capacitors have been studied. For the first time, electron‐heating‐induced trap generation and interface state creation is separated from those defects created through electron‐hole pair recombination. The midgap interface state density is observed to increase linearly with the number of recombination events and approaches saturation in the mid 1011 eV−1 cm−2 range for trapped hole densities greater than about 1012 cm−2. However, the total integrated interface state density, although showing a similar net increase to that of the midgap interface state density, does not saturate for the largest trapped hole densities introduced in this work. For hot‐electron‐induced defects, a dramatic increase in the interface state generation rate is observed for average electric fields above a threshold of 1.5×106 V cm−1. An increase in the electron trapping rate above the heating thresho...

Unpinned gallium oxide/GaAs interface by hydrogen and nitrogen surface plasma treatment

The Fermi level at the Ga oxide/GaAs interface has been unpinned by rf plasma cleaning the GaAs surface in H2 and N2. Following plasma cleaning, a Ga oxide film is reactively electron beam deposited onto the substrate. Metal‐oxide‐semiconductor (MOS) capacitors fabricated on these structures show good high‐frequency capacitance‐voltage characteristics. This indicates that the density of interface states has been reduced to ∼1011 eV−1 cm−2. The MOS capacitors are found to be stable in air after several months.