D. B. Janes

Self-Assembly of a Two-Dimensional Superlattice of Molecularly Linked Metal Clusters

Close-packed planar arrays of nanometer-diameter metal clusters that are covalently linked to each other by rigid, double-ended organic molecules have been self-assembled. Gold nanocrystals, each encapsulated by a monolayer of alkyl thiol molecules, were cast froma colloidal solution onto a flat substrate to form a close-packed cluster monolayer. Organic interconnects (aryl dithiols or aryl di-isonitriles) displaced the alkyl thiol molecules and covalently linked adjacent clusters in the monolayer to form a two-dimensional superlattice of metal quantum dots coupled by uniform tunnel junctions. Electrical conductance through such a superlattice of 3.7-nanometer-diameter gold clusters, deposited on a SiO2 substrate in the gap between two gold contacts and linked by an aryl di-isonitrile [1,4-di(4-isocyanophenylethynyl)-2-ethylbenzene], exhibited nonlinear Coulomb charging behavior.

Collective computational activity in self-assembled arrays of quantum dots: a novel neuromorphic architecture for nanoelectronics

We describe a new class of nanoelectronic circuits which exploits the charging behavior in resistively/capacitively linked arrays of nanometer-sized metallic islands (quantum dots), self-assembled on a resonant tunneling diode, to perform neuromorphic computation. These circuits produce associative memory effects and realize the additive short-term memory (STM) or content addressable memory (CAM) models of neural networks without requiring either large-area/high-power operational amplifiers, or massive interconnectivity between devices. Both these requirements had seriously hindered the application of neural networks in the past. Additionally, the circuits can solve NP-complete optimization problems (such as the traveling salesman problem) using single electron charge dynamics, exhibit rudimentary image-processing capability, and operate at room temperature unlike most quantum devices. Two-dimensional (2D) processors, with a 100/spl times/100 pixel capacity, can be fabricated in an area of 10/sup -8/ cm/sup 2/ leading to unprecedented functional density. Possible routes to synthesizing these circuits, employing self-assembly, are also discussed.

Molecular Beam Epitaxy of Nonstoichiometric Semiconductors and Multiphase Material Systems

Abstract When arsenides are grown by molecular beam epitaxy at low substrate temperatures, as much as 2% excess arsenic can be incorporated into the epilayer. This excess arsenic is in the form of antisites, but there is also a substantial concentration of gallium vacancies. With anneal, there is a significant decrease in the arsenic antisite and gallium vancancy concentrations as the excess arsenic precipitates. With further anneal, the arsenic precipitates coarsen. This combination of low substrate temperature molecular beam epitaxy and a subsequent anneal results in a broad spectrum of materials, from highly defected epilayers to a two-phase system of semimetallic arsenic precipitates in an arsenide semiconductor matrix. These materials exhibit some very interesting and useful electrical and optical properties.

Nanoelectronic architecture for Boolean logic

A nanoelectronic implementation of Boolean logic circuits is described where logic functionality is realized through charge interactions between metallic dots self-assembled on the surface of a double-barrier resonant tunneling diode (RTD) structure. The primitive computational cell in this architecture consists of a number of dots with nearest neighbor (resistive) interconnections. Specific logic functionality is provided by appropriate rectifying connections between cells. We show how basic logic gates, leading to combinational and sequential circuits, can be realized in this architecture. Additionally, architectural issues including directionality, fault tolerance, and power dissipation are discussed. Estimates based on the current-voltage characteristics of RTDs and the capacitance and resistance values of the interdot connections indicate that static power dissipation as small as 0.1 nW/gate and switching delay as small as a few picoseconds can be expected. We also present a strategy for fabricating/synthesizing such systems using chemical self-organizing/self-assembly phenomena. The proposed synthesis procedure utilizes several chemical self-assembly techniques which have been demonstrated recently, including self-assembly of uniform arrays of close-packed metallic dots with nanometer diameters, controlled resistive linking of nearest neighbor dots with conjugated organic molecules and organic rectifiers.

Room temperature Coulomb blockade and Coulomb staircase from self‐assembled nanostructures

The self‐assembly of well‐characterized, nanometer‐size Au clusters into ordered monolayer arrays spanning several microns has been achieved. Techniques to insert molecular wires to link adjacent clusters in the self‐assembled array have also been developed. ‘‘Unit cell’’ nanostructures formed from individual Au clusters supported on a self‐assembled monolayer film of the double‐ended thiol molecule p‐xylene‐α,α′‐ dithiol show evidence for reproducible single electron effects at room temperature when studied by scanning tunneling microscopy. From these measurements, estimates for the electrical resistance of a single molecule can be obtained. The experimental values for this resistance are in reasonable agreement with theoretical calculations using the Landauer approach.

Stochastic interconnect modeling, power trends, and performance characterization of 3-D circuits

Three-dimensional (3-D) technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into 3-D circuit architecture and performance. One of the purposes of realizing 3-D integration is to reduce the interconnect complexity and delay of two dimensions (2-D), which are widely considered as the barriers to continued performance gains in future technology generations. Thus, understanding the interconnect and its related issues, such as the impact on circuit performance, is key to 3-D circuit applications. In this paper, we present a stochastic 3-D interconnect model and study the impact of 3-D integration on circuit performance and power consumption. To model 3-D interconnect, we divide 3-D wires into two parts (horizontal wires and vertical wires) and derive their stochastic distributions. Based on those distributions, we estimate the delay distribution. We show that 3-D structures effectively reduce the number of long delay nets, significantly reduce the number of repeaters, and dramatically improve circuit performance. With 3-D integration, circuits can be clocked at frequencies much higher (double or even triple) than 2-D.

Electronic Properties of Metallic Nanoclusters on Semiconductor Surfaces: Implications for Nanoelectronic Device Applications

We review current research on the electronic properties of nanoscale metallic islands and clusters deposited on semiconductor substrates. Reported results for a number of nanoscale metal-semiconductor systems are summarized in terms of their fabrication and characterization. In addition to the issues faced in large-area metal-semiconductor systems, nano-systems present unique challenges in both the realization of well-controlled interfaces at the nanoscale and the ability to adequately characterize their electrical properties. Imaging by scanning tunneling microscopy as well as electrical characterization by current-voltage spectroscopy enable the study of the electrical properties of nanoclusters/semiconductor systems at the nanoscale. As an example of the low-resistance interfaces that can be realized, low-resistance nanocontacts consisting of metal nanoclusters deposited on specially designed ohmic contact structures are described. To illustrate a possible path to employing metal/semiconductor nanostructures in nanoelectronic applications, we also describe the fabrication and performance of uniform 2-D arrays of such metallic clusters on semiconductor substrates. Using self-assembly techniques involving conjugated organic tether molecules, arrays of nanoclusters have been formed in both unpatterned and patterned regions on semiconductor surfaces. Imaging and electrical characterization via scanning tunneling microscopy/spectroscopy indicate that high quality local ordering has been achieved within the arrays and that the clusters are electronically coupled to the semiconductor substrate via the low-resistance metal/semiconductor interface.

Guided self-assembly of Au nanocluster arrays electronically coupled to semiconductor device layers

We report the controlled deposition of close-packed monolayer arrays of ∼5-nm-diam Au clusters within patterned regions on GaAs device layers, thus demonstrating guided self-assembly on a substrate which can provide interesting semiconductor device characteristics. Uniform nanometer scale ordering of the clusters is achieved by a chemical self-assembly process, while micron scale patterning is provided by a soft lithographic technique. Scanning tunneling microscope imaging and current–voltage spectroscopy indicate the Au nanoclusters are strongly coupled electronically into the underlying semiconductor substrate while exhibiting only weak electronic coupling in the lateral plane.

Inhibited oxidation in low‐temperature grown GaAs surface layers observed by photoelectron spectroscopy

The surface oxidation characteristics of a GaAs layer structure consisting of a thin (10 nm) layer of low‐temperature‐grown GaAs (LTG:GaAs) on a heavily n‐doped GaAs layer, both grown by molecular beam epitaxy, have been studied using x‐ray photoelectron spectroscopy (XPS). Between the layer growth and XPS characterization, the unannealed LTG:GaAs sample and a control sample without the LTG:GaAs surface layer were exposed to the atmosphere. The rate of surface oxidation in the sample with a LTG:GaAs surface layer was significantly lower than the oxidation rate of the control sample. This direct observation of inhibited oxidation confirms the surface stability of comparable structures inferred from earlier electrical measurements. The inhibited surface oxidation rate is attributed to the bulk Fermi‐level pinning and the low minority carrier lifetime in unannealed LTG:GaAs.

Error analysis leading to design criteria for transmission line model characterization of ohmic contacts

The transmission line model (TLM) is a standard method for planar specific contact resistance measurement. Although widely used, the accuracy of a measurement is typically not stated. In addition to contributions from random errors, there can be substantial contributions from systematic errors in typical TLM measurements. In this paper, we develop an analytical model for the experimental uncertainty from the fundamental TLM expressions in order to understand and calculate the uncertainty associated with the specific contact resistance and sheet resistance derived by the TLM method. The experimental uncertainties in measured resistances, together with the pad width and pad spacing, are the dominant contributions to the total uncertainty. Analytical expressions for relative random and systematic uncertainties in contact resistance and sheet resistance are developed in terms of the error contributions and the parameters of the TLM geometry. Expressions for minimum uncertainty, with associated optimum widths and sheet resistances, serve as a basis for the design of TLM structures with minimum uncertainty. The model quantifies the increase in relative uncertainty associated with decreasing contact resistance. Simulations of uncertainty under various sheet resistance, contact resistance, and pad width are implemented and uncertainties are calculated for realistic data sets.