D. Bortolato

Global Trigger and Readout System for the AGATA Experiment

AGATA is a 4-pi array of high purity Ge detectors for in-beam gamma-ray spectroscopy based on the novel concepts of pulse shape analysis (PSA) and gamma-ray tracking. Tracking and PSA require the concurrent digitization-at a sampling rate of 100 Msamples/s-of preamplifier signals of the 36-fold segmented Ge crystals composing the array. Locally digitized data are optically transferred to remote pre-processing nodes for pulse energy computation. The design of the front-end readout and level-1 (L1) trigger in AGATA follows a synchronous pipeline model: the detector data are stored in pipeline buffers at the global AGATA frequency, waiting the global L1 decision. A global timing system provides a reference clock and time tag to the digitizers and the pre-processing units by means of a tree of optically connected timing units. Pre-processing nodes are integrated in advanced TCA-based carrier cards with full mesh connectivity in the backplane and read-out through pci-express based optical links. The front-end data readout and its integration in the global trigger and synchronization system will be described.

Global Trigger and Readout System for the AGATA experiment

AGATA is a 4-pi array of HP-Ge detectors for in-beam gamma-ray spectroscopy based on the novel concepts of pulse shape analysis (PSA) and gamma-ray tracking. Tracking and PSA require the concurrent digitization -at a sampling rate of 100 Msamples/s -of preamplifier signals of the 36-fold segmented Ge crystals composing the array. Locally digitized data are optically transferred to remote pre-processing nodes for pulse energy computation. The design of the front-end readout and level-1 (L1) trigger in AGATA follows a synchronous pipeline model: the detector data are stored in pipeline buffers at the global AGATA frequency, waiting the global L1 decision. A global timing system provides a reference clock and time tag to the digitizers and the pre-processing units by means of a tree of optically connected timing units. Pre-processing nodes are integrated in ATCA-based carrier cards with full mesh connectivity in the backplane and read-out through pci-express based optical links. Front-end data readout and its integration with the global trigger and synchronization system will be described.

Performance of the Fully Digital FPGA-Based Front-End Electronics for the GALILEO Array

In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. This work presents the first results of the digital FEE system coupled with a GALILEO germanium detector, which has demonstrated the capability to achieve an energy resolution of 1.530/00 at an energy of 1.33 MeV, similar to the one obtained with a conventional analog system. While keeping a good performance in terms of energy resolution, digital electronics will allow to instrument the full GALILEO array with a versatile system with high integration and low power consumption and costs.

Development of the control card for the digitizers of the second generation electronics of AGATA

In this work, the features and development process of the novel control card for the digitizers of AGATA are presented. The board is part of the new hardware proposed for the electronic system of the experiment. In particular, the control card provides the sampling clock for the digitizers, contributes to the synchronization of the digital data and performs the slow control of its associated digitizer cards.

A PCI Express optical link based on low-cost transceivers qualified for radiation hardness

In this paper we want to demonstrate that an optical physical medium is compatible with the second generation of PCI Express. The benefit introduced by the optical decoupling of a PCI Express endpoint is twofold: it allows for a geographical detachment of the device and it remains compliant with the usual PCI accesses to the legacy I/O and memory spaces. We propose two boards that can bridge the PCI Express protocol over optical fiber. The first is a simple optical translator while the second is a more robust switch developed for connecting up to four devices to a single host. Such adapters are already working in the control and data acquisition system of a particle detector at CERN and hence they had been qualified for radiation hardness. The positive outcomes of the radiation tests of four types of off-the-shelf transceivers are finally reported.

Graphical user interface for serial protocols through a USB link

In this work, a graphical user interface to communicate with three common serial protocols is presented. With one tool, the user may be able to control several evaluation boards from different manufacturers or evaluate and program integrated circuits of complex board prototypes. It provides a user-friendly interface to communicate with several chips using the USB port. The program has been used for the first stages in the qualification process of electronic boards for the Advanced GAmma Tracking Array (AGATA).

High-spin structure in K-40

High-spin states of K-40 have been populated in the fusion-evaporation reaction C-12(Si-30,np)K-40 and studied by means of gamma-ray spectroscopy techniques using one triple-cluster detector of the ...

New LLRF control system at LNL

The Low-level Radio Frequency (LLRF) control system for linear accelerator at Legnaro National Laboratories (LNL) of INFN is being upgraded by a new digital Radio Frequency (RF) controller. This controller is critical to keep phase, amplitude and frequency stability of the RF field in Quarter Wave Resonator (QWR) cavities of the linear accelerator. These cavities work in superconducting condition. The resonance frequency of low beta cavities is 80 MHz, while medium and high beta cavities resonate at 160 MHz. Each RF controller can control at the same time eight different cavities. The RF signals picked-up from the cavities are sampled by RF ADCs. The digitized signals are fed into a field programmable gate array (FPGA) which implements the control loop. The signals processed by the FPGA are in-phase/quadrature modulated and sent to power amplifiers and hence to the cavities. The main feature of the new control system is an all-digital control loop that originates from direct sampling of the antenna RF signal. In-phase and quadrature components are obtained by a suitable choice of the undersampling frequency, while control of the field and phase in the cavity is based on a digital Complex Phase Modulator (CPM). This paper presents the FPGA firmware, the acquisition techniques and the performances of the new RF controller.

An I/O controller for real time distributed tasks in particle accelerators

SPES is a second generation ISOL radioactive ion beam facility in construction at the INFN National Laboratories of Legnaro (LNL). Its distributed control system embeds custom control in almost all instruments or cluster of homogeneous devices. Nevertheless, standardization is an important issue that concerns modularity and long term maintainability for a facility that has a life span of at least twenty years. In this context, the research project presented in this paper focuses on the design of a custom Input Output Controller (IOC) which acts as a local intelligent node in the distributed control network and is generic enough to perform several different tasks spanning from security and surveillance operations, beam diagnostic, data acquisition and data logging, real-time processing and trigger generation. The IOC exploits the Computer On Module (COM) Express standard that is available in different form factors and processors, fulfilling the computational power requirement of varied applications. The Intel x86_64 architecture makes software development straightforward, easing the portability. The result is a custom motherboard with several application specific features and generic PC functionalities. The design is modular to a certain extent, thanks to an hardware abstraction layer and allows the development of soft and hard real-time applications by means of a real-time Operating System and the on-board FPGA closely coupled to the CPU. Three PCIe slots, a FPGA Mezzanine Card (FMC) connector and several general-purpose digital/analog inputs/outputs enable functionality extensions. An optical fiber link connected to the FPGA is an high speed interface for high throughput data acquisitions or time-sensitive applications. The power distribution complies the AT standard and the whole board can be powered via Power Over Ethernet (POE+) IEEE 802.3at standard. Networking and device-to-cloud connectivity are guaranteed by a gigabit Ethernet link. The design, performance of the prototypes and intended usage will be presented.

Fully digital FPGA-based Front-End Electronics for the GALILEO array

In this work we present the fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. The digital processing of the data from the GALILEO germanium detectors has demonstrated the capability to achieve an energy resolution of 1.53% at an energy of 1.33 MeV.