D. Campbell

A 66 MHz, 32-channel analog memory circuit with data selection for fast silicon detectors

Abstract An analog memory array with 64 memory cells for each channel has been designed and manufactured in CMOS. A new skip logic controller allows to write at 66 MHz without dead time and to read out at a lower frequency simultaneously. The input circuit is charge-sensitive and integrates continuously. Pedestal nonuniformity is 1.4 mV rms from cell-to-cell and 3.5 mV rms between channels. The linearity range is −2.5 to +1.5 V, which corresponds to 11 bits. The chip has been used in a particle detection test.

DYN1: a 66 MHz front end analog memory chip with first level trigger capture for use in future high luminosity particle physics experiments

DYN1 is a 32 channel, 128 cell analog memory with continuous write and read access. The chip amplifies the detector signals and integrates the signal currents onto capacitors within the memory during each bunch crossing interval. Dense dynamic logic circuitry accepts multiple first level triggers, freezes the corresponding analog data and stores their addresses in an external FIFO. The triggered data can then be read out at leisure whilst simultaneously sampling and storing new triggered events. A first level trigger latency of up to 2 μs is accepted at the maximum LHC clock frequency of 66 MHz. The chip shows an overall gain of 48.2 mV/25000 e−. The mean channel noise is 4.5 mV and the pedestal variation from cell to cell within one channel is 1.9 mV. The total dynamic range has been measured at 4.6 V giving a resolution of 11 bits (0.05%) for the memory itself.

The UA1 upgrade calorimeter trigger processor

Abstract The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-levl trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no dead time. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic shower, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecess or, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider.

Characteristics of a 'HARP' signal processor with analog memory operated with segmented silicon detectors

A 32 channel analog VLSI detector readout chip (HARP32) with an input charge preamplifier, a 64-cell current integrating analog memory in each channel and a common analog multiplexer, has been used in a test beam with segmented silicon detectors. The device was operated at the LHC clock speed of 66 MHz. The different pedestal variations seen at the output are analyzed: the input noise /spl sigma//sub n/ amounts to 2.8mV r.m.s., the pedestal non-uniformity in channel /spl sigma//sub ped/ to 1.2 mV r.m.s., the channel to channel pedestal variation /spl sigma//sub ch/ to 4.0 mV r.m.s., and an output baseline shift /spl sigma//sub obs/ of 3.5 mV r.m.s has been observed. >

Electronics and readout of a large area silicon detector for LHC

Abstract The purpose of the RD2 project is to evaluate the feasibility of a silicon tracker and/or preshower detector for LHC. Irradiation studies with doses equivalent to those expected at LHC have been performed to determine the behavior of operational parameters such as leakage current, depletion voltage and charge collection during the life of the detector. The development of fast, dense, low power and low cost signal processing electronics is one of the major activities of the collaboration. We describe the first fully functional integrated analog memory chip with asynchronous read and write operations and level 1 trigger capture capabilities. A complete test beam system using this analog memory chip at 66 MHz has been successfully operated with RD2 prototype silicon detectors during various test runs. The flexibility of the electronics and readout have allowed us to easily interface our set-up to other data acquistion systems. Mechanical studies are in progress to design a silicon tracking detector with several million channels that may be operated at low (0–10°C) temperature, while maintaining the required geometrical precision. Prototype readout boards for such a detector are being developed and simulation studies are being performed to optimize the readout architecture.

UA1 upgrade first-level calorimeter trigger processor

Abstract A new first-level trigger processor has been built for the UA1 experiment on the Cern SppS Collider. The processor exploits the fine granularity of the new UA1 uranium-TMP calorimeter to improve the selectivity of the trigger. The new electron trigger has improved hadron jet rejection, achieved by requiring low energy deposition around the electromagnetic cluster. A missing transverse energy trigger and a total energy trigger have also been implemented.

The development of a rad-hard CMOS chip for the binary readout of the ATLAS semiconductor tracker

A new version of the ABC (Atlas Binary Chip) has been submitted to Honeywell. The design contains many enhancements over the original ABC: new DAC circuitry for improved radiation hardness, faster and more robust logic parts and new interface elements to the CAFE chip. Each of these design elements will be described in detail as well as the status of the ongoing test program. Additionally, plans for production testing of ABC’s will be presented.

Implementation of a 66 MHz analog memory as a front end for LHC detectors

We describe the front end signal processing chip (HARP) being developed by the RD2 collaboration for LHC detectors. The HARP chip, based around an analog memory, will provide data storage at LHC rates for 2 [mu]sec and allow stored data to be accessed for trigger rates of up to 50--100 KHz. We have tested two different prototypes of the final chip as front end for silicon detectors, using a Sr90 source and high energy pions and electrons from the CERN-SPS test beam.

Readout electronics development for the ATLAS silicon tracker

Abstract We present the status of the development of the readout electronics for the large area silicon tracker of the ATLAS experiment at the LHC, carried out by the CERN RD2 project. Our basic readout concept is to integrate a fast amplifier, analog memory, sparse data scan circuit and analog-to-digital convertor (ADC) on a single VLSI chip. This architecture will provide full analog information of charged particle hits associated unambiguously to one LHC beam crossing, which is expected to be at a frequency of 40 MHz. The expected low occupancy of the ATLAS inner silicon detectors allows us to use a low speed (5 MHz) on-chip ADC with a multiplexing scheme. The functionality of the fast amplifier and analog memory have been demonstrated with various prototype chips. Most recently we have successfully tested improved versions of the amplifier and the analog memory. A piecewise linear ADC has been fabricated and performed satisfactorily up to 5 MHz. A new chip including amplifier, analog memory, memory controller, ADC, and data buffer has been designed and submitted for fabrication and will be tested on a prototype of the ATLAS silicon tracker module with realistic electrical and mechanical constraints.

Fast two dimensional cluster finding in particle physics

The cluster finding module (CFM) is part of the UA1 trigger processor. The CFM detects and counts two-dimensional clusters of electromagnetic particles. This process requires 75 ns for detection of either isolated or nonisolated clusters and 75 ns to count them. This is equivalent to a peak computational rate of 11000 MIPS (million instructions per second) per module (3000 MIPS average). The required high logic density and speed are achieved by using programmable array logic devices within a pipelined system. The design has been strongly influenced by the need for in-situ computer testing. >