D. D. Brown

Stress‐induced voiding and electromigration

Thermal stress induced voiding provides an effective nucleation mechanism for the electromigration induced damage and failure of narrow, passivated metal lines. Small voids are trapped at grain and phase boundaries, where they grow under a current. Growth rates are determined by the local flux divergencies and the current induced stress distribution. After reaching a critical size, some voids begin to migrate and coalesce, eventually leading to line failure. A model is outlined, which is capable of explaining a large number of experimental observations and offers a basis for the prediction of failure statistics.

Stress evolution during stress migration and electromigration in passivated interconnect lines

Differences between the coefficients of thermal expansion of a narrow metal line and surrounding chip and passivation lead to the establishment of very large tensile stresses, which can only be effectively relaxed through the formation and growth of voids when the passivation remains intact. Furthermore, an electromigration induced atomic flux will lead to simultaneous void growth and accumulation of atoms at appropriate flux divergences. For a given current and microstructures (including void locations) a unique relationship can be established between the time, stress distributions and the corresponding void volumes. We model the stress evolution in passivated near‐bamboo lines to account for the synergistic effects of stress migration and electromigration on void growth and open failure under various combinations of temperature, current, microstructure, and the presence of W‐studs/vias.

Predicting and Comparing Electromigration Failure for Different Test Structures

Electromigration and stress migration are important reliability concerns in the semiconductor industry. Relative and absolute assessments of lifetimes generally rely on the accelerated testing of ‘standard’ test structures. However, the sensitivity to various important electromigration phenomena is found to depend strongly on the type of test structure. Two common structures for electromigration testing are (i) a long line with large pads at either end and (ii) a more realistic interconnect line with W-studs at the line end. The effects of (a) different flux divergences at the line end, (b) interfacial diffusion, and (c) Cu-depletion generally result in different lifetimes for the two types of test structures under the same testing conditions. In this paper, we compare void growth rates and mean times to failure for both types of test structure taking these effects into account. Our results are used to explain differences in MTF values reported in the literature for different test structures.

Mechanical Properties of Plated Copper

Both electrodeposited and electroless copper are widely used in the electronics industry to form signal lines and plated-through holes in printed circuit cards and boards. Because of widely differing thermal expansion coefficients of copper and of the ceramic and polymeric substrates, large mechanical stresses develop in the metallization during thermal cycles, as e.g. during solder reflow. To safeguard against premature fracture it is imperative that the metallization is sufficiently ductile. Plated thin foil copper of poor ductility is known to be susceptible to cracks in plated-through holes which, besides causing problems in the manufacture, poses a threat to device reliability in service. In this paper we show that such cracks arise as a combination of reduced ductility due to presence of initial porosity in copper and due to grain boundary sliding and diffusional cavity growth during the soldering cycle. We emphasize that there exists strong interactions between these ductility reducing effects, such that their coupled action may exceed the effect when each mechanism operates independently. We review recent research on deformation and fracture of bulk and plated copper between RT and 300°C. Finally, we briefly discuss approaches to improve mechanical properties of plated thin foil copper.

The Effect of Thermally Induced Stresses on Electromigration Lifetime Of Near-Bamboo Interconnects

Thermal stresses may affect significantly electromigration induced open failures in nearbamboo interconnect structures ending in W-vias. Based on a physical model, we investigate the thermal stress effects on void nucleation, on early failures due to grain boundary diffusion, and on longer term bulk diffusion dominated failures. It is shown that thermal stress is all important as far as early failures are concerned. In particular, during accelerated tests and service, the early failures, when occur, arise due to stress and current directed grain boundary diffusion along grain clusters. In the accelerated test, bulk diffusion dominated void growth at vias determines the long term failures while during service bulk diffusion contribution is usually negligibly small within time frames of practical interest. Because the dominant failure mechanisms change, the extrapolation from the accelerated tests to the service conditions is not straight-forward.

Statistics of stress migration and electromigration failures of passivated interconnect lines

We outline a microstructure‐based statistical model for passivated near‐bamboo interconnect structures to obtain quantitative predictions of stress migration and electromigration failures, and their stress, temperature and current dependence. In particular, we find the failure distributions to be multimodal, and the mode responsible for failure at the early failure level is often not significant in the experimentally accessible regime of the cumulative failure, about 5–95%. We show that the early and longer term failure modes, both at vias and the straight line portions, depend differently on the stress, temperature and current density, which necessitates devising improved extrapolation procedures for the prediction of the time to early failure in service conditions. As far as electromigration lifetimes are concerned, the effect of refractory metal barrier layers is simply to allow larger void sizes at failure.

Thermal Stress Induced Void Formation in Narrow Passivated Cu Lines

0.75–3 μm wide copper lines encased in a thin adhesion layer of Al or Cr were passivated at 300°C and annealed at 400°C. The passivation was then removed and the lines examined in a scanning electron microscope. The development of thermal stress induced voiding was found to depend primarily on aging conditions and adhesion.

Stress-Voiding and Electromigration in Multilevel Interconnect Metallizations

Stress-voiding or stress migration (SM), and electromigration (EM) are urgent problems in ULSI microcircuits with features in the submicron range. Severe stress-voiding arises in multilevel metallizations because of the high constraint offered by the refractory metal layers, the ceramic insulation, and the rigid contact and via structures which prevent plastic relaxation of the thermally induced stresses. Also, W-plugs and/or refractory barrier layers block entirely the EM flux, resulting in an enhanced probability of EM damage. We review the physical bases of a recently introduced unified SM and EM model [1,2]. We apply the model to an interconnect line confined by vias at both ends and derive equations which explicitly show the effects of external conditions and microstructural parameters on the evolution of SM and EM damage. Particularly we analyze the effects of Cu depletion on void growth rate at vias. We also show how the shifts in the line resistance are related to void growth. Finally we demonstrate that the model predictions compare well with the recently published experimental EM data.