D. Dzahini

Auto-zero stabilized CMOS amplifiers for very low voltage or current offset

In this paper, we present two amplifiers designed in CMOS technology and including an auto-zero architecture for very low offset control. The first design is a high precision operational amplifier focusing on the voltage offset. It is a continuous time auto-zero stabilized architecture, that leads to a typical input offset voltage of 2 /spl mu/V-100nV//spl deg/C. The amplifier with its output buffer consumes 5mW at a supply voltage of +/- 2.5V. The gain bandwidth product is 2MHz while the slew rate is respectively -6V/ /spl mu/s and +8.8V/ /spl mu/s on 10pF with 10K/spl Omega/ load. This amplifier is suitable for the control of large dynamic (>10/sup 5/) calibration signal, and for very low DC signal instrumentation. The second design is a current mode charge pulse amplifier based on a second generation positive current conveyor topology (CCII). The bandwidth, the dynamic range and the output impedance have been optimized using an enhanced cascode current mirror. The preamplifier provides two outputs: one for the signal integration, and another going through a current comparator for a digital counting flow. The double hit resolution is less than Ins. An auto-zero compensation has been added to this preamplifier to control its output current offset down to 60nA. The total power dissipation (preamplifier + offset cancelation + comparator) is less than 1mW. This second amplifier has been designed for low power space applications, especially EUSO (Extreme Universe Space Observatory), which use multianode PMT in the configuration of a large gate time (2.5 /spl mu/s) open for charge integration.

Radiation qualification of the front-end electronics for the readout of the ATLAS liquid argon calorimeters

The ATLAS detector has been built to study the reactions produced by the Large Hadron Collider (LHC). ATLAS includes a system of liquid argon calorimeters for energy measurements. The electronics for amplifying, shaping, sampling, pipelining, and digitizing the calorimeter signals is implemented on a set of front-end electronic boards. The front-end boards are installed in crates mounted between the calorimeters, where they will be subjected to significant levels of radiation during LHC operation. As a result, all components used on the front-end boards had to be subjected to an extensive set of radiation qualification tests. This paper describes radiation-tolerant designs, radiation testing, and radiation qualification of the front-end readout system for the ATLAS liquid argon calorimeters.

Construction and test of the first two sectors of the ATLAS barrel liquid argon presampler

The electromagnetic (e.m.) calorimeter of the ATLAS experiment for the Large Hadron Collider will be a sampling liquid argon accordion calorimeter. To achieve sufficient energy resolution, it is necessary to correct for the energy loss in the material upstream of the calorimeter. For this purpose, a separate presampler detector fixed on the inner face of the e.m. calorimeter, in the same cryostat, is being built by the ATLAS collaboration. Two presampler sectors have already been built and tested in their final version. The geometry of the detector and the various steps of its construction are reviewed. The hardware performance of the detector measured both at CERN and at the ISN-Grenoble (specific test bench) is discussed. It is concluded that the presampler will adequately fulfill its role for future operation at the CERN Large Hadron Collider.

A Low Power and Low Signal 5-bit 25 MS/s Pipelined ADC for Monolithic Active Pixel Sensors

For CMOS monolithic active pixels sensor readout, we developed a 5 bit low power analog to digital converter using a pipelined architecture. A non-resetting sample and hold stage is included to amplify the signal by a factor of 4. Due to the very low level of the incoming signal, this first stage compensates both the amplifier offset effect and the input common mode voltage dispersion. The converter consists of three 1.5 bit sub-ADC and a 2 bit flash. We present the results of a prototype, made of eight ADC channels. The maximum sampling rate is 25 MS/s. The total DC power consumption is 1.7 mW/channel on a 3.3 V supply voltage recommended for the process. But at a reduced 2.5 V supply, it consumes only 1.3 mW. The size of each ADC channel layout is only . This corresponds to the pitch of two pixel columns each one would be 20 wide. The full analog part of the converter can be quickly switched to a standby idle mode in less than 1 mum; thus reducing the power dissipation to a ratio better than 1/1000. This fast shutdown is very important for the ILC vertex detector as the total DC power dissipation becomes directly proportional to the low beam duty cycle.

NECTAr0, a new high speed digitizer ASIC for the Cherenkov Telescope Array

H.E.S.S. and MAGIC experiments have demonstrated the high level of maturity of Imaging Atmospheric Cherenkov Telescopes (IACTs) dedicated to very-high-energy gamma ray astronomy domain. The astroparticle physics community is preparing the next generation of instruments, with sensitivity improved by an order of magnitude in the 10 GeV to 100 TeV range. To reach this goal, the Cherenkov Telescope Array (CTA) will consist in an array of 50–100 dishes of various sizes and various spacing, each equipped with a camera, made of few thousands fast photo-detectors and its associated front-end electronics. The total number of electronics channels will be larger than 100,000 to be compared to the total of 6,000 channels of the 5-telecopes H.E.S.S. / H.E.S.S.-II array. To decrease the overall CTA cost, a consequent effort should be done to lower the cost of the electronics while keeping performance at least as good as the one demonstrated on the current experiments and simplifying its maintenance. This will be allowed by mass production, use of standardized modules and integration of front-end functions in ASICs. The 3-year NECTAr program started in 2009 addresses these two topics. Its final aim is to develop and test a demonstrator module of a generic CTA camera. The paper is mainly focused on one of the main components of this module, the NECTAr ASIC which samples the photo-detector signal in a circular analog memory at several GSPS and digitizes it over 12 bits after having received an external trigger.

A low power 12-bit and 25-MS/s pipelined ADC for the ILC / ECAL integrated readout

The design of a fully integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here two prototypes of a 12-bit 25-MS/s analog to digital converter using a pipelined architecture. The first one is composed of ten 1.5 bit stages and a 2 bit full flash ADC which produces the least significant bits (LSB) of the converter. The second prototype is composed of a multi-bit first stage of 2.5 bits, followed by seven 1.5 bit stages as a back-end converter and a 3 bit full flash. A CMOS 0.35 μm process is used, and the dynamic range covered is 2V. The analog part of the converter can be quickly (a couple of μs) switched to a standby mode that reduces the DC power dissipation by a ratio of 1/1000. The total power dissipation of the first prototype is 37mW. For the second chip, the size of the converter’s layout including the digital correction stage is only 1.9mm*0.9mm, and the total power dissipation is 42mW.

A low power 12-bit and 30-MS/s pipeline analog to digital converter in 0.35μm CMOS

The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash. A CMOS 0.35 mum process is used, and the dynamic range covered is 2 V. The analog part of the converter can be quickly (a couple of mus) switched to a standby mode that reduces the DC power dissipation by a ratio of 1/1000. The size of the converterpsilas layout including the digital correction stage is only 1.7 mm*0.6 mm, and the total dc power dissipation is 35 mW.

A very low offset voltage auto-zero stabilized CMOS operational amplifier

A high precision operational amplifier has been developed in a standard .8μ CMOS process. A continuous time auto− zero stabilized architecture was used, that leads to a typical input offset voltage less than 2μV −100nV/°C. The amplifier with its output buffer consumes 5mW at a supply voltage of +/− 2.5V. The gain bandwidth product is 2MHz while the slew rate is respectively −6V/μS and +8.8V/μS on 10pF with 10KΩ load. This amplifier is suitable for the control of large dynamic (>10E5) calibration signal, and for very low signal instrumentation. I) INTRODUCTION Offset is a very important parameter for many applications: high energy physics calibration systems, low signal sensor interfaces, high accuracy instrumentation. A careful layout design could be combined with internal trimming to reduce the offset from a few mV down to around 100μV. The screening steps required for such a strategy could take a long time and consequently would be very expensive. Moreover, in many applications, one has a concern with the offset drift (with the time, temperature, power supply etc..). Therefore auto−zero stabilization architecture is a more efficient and elegant solution to the offset cancellation. CMOS technology is suitable for such a design, due to its analog switch capabilities, lower power architectures and low cost. In this paper, is presented the design of an auto−zero amplifier in a CMOS standard process using a folded cascode architecture. II) AUTO−ZERO AMPLIFIER: OVERVIEW A continuous auto zero amplifier requires two internal amplifiers. The block diagram is shown in figure 1. The so called ’Main amplifier’ is unswitched and continuously available for the incoming signal amplification. figure 1: Auto zero amp, block diagram There are two alternating successive phases for the offset cancellation. During the first one, the ’Null’ amplifier is disconnected from the signal path for its auto correction. A correction signal Vcn is generated and held on Cn external capacitors connected at the the auxiliary inputs. During the second phase, the Null amplifier is reconnected to the Main and senses its input offset. Another correction voltage Vcm is generated this way and stored on capacitor Cm for the Main amplifier correction. Each internal amplifier could be modelized with two differential inputs: a primary and an auxiliary one as in figure 2 . figure 2 Internal amplifier model The output signal can be expressed as: V s A s V A s V A s V i d i d o s 0 ( ) ( ). ’( ). ’ ( ). = + + With the assumption that the primary and auxiliary inputs are combined in the first stage of the amplifier, their respective dominant poles will be very closed. Then we could define a constant ratio α between the open loop gains: α = A0(s) / A’(s) Consider now the full auto−zero amplifier in a feedback loop as in figure 3 ,where Vosm and Vosn are respectively the residual offset of the Main and Null internal amplifiers. During phase φ1, S1 short−circuit the Null amplifier and its output charges the capacitor Cn via S2 to the the Vcn value . V A A V V V V c n n o s c n o s c n n n n n = − + + ≅ − + 1 ’ ∆ ∆ α ∆Vc n is a perturbation voltage related to the charge injection , noise etc.. Figure:3 Simulation configuration During the phase f2, the Null amplifier senses the offset of the Main and stores the resulting control voltage Vcm on the capacitor Cm. In a feedback configuration as shown in figure 3 one obtains V A V V V A V o u t m o s m c m m = − − + + − ( ) ’ and V A V V V A V A V V V A V c n os n c n n os n c m n n n n = − − − ≅ − − − + − + − ( ) ’ ( ) ’ α ∆ In the case Vout=0 and V+ − V− = Vos(2) (offset during the phase φ2), one can deduce V V V A V o s m o s n o s n c n m n n ( ) 2 ≅ + + α α α ∆ with ( ’ ) A A A n m m >> During the next φ1 phase, the offset will become. V V V o s o s c m m ( ) ( ) 1 2 = − ∆ α leading into: V V V A V V o s m n o s o s n c n c m m m n n ( ) ( ) ’ 1 = + + − α α α α ∆ ∆ After many iterations of phases φ1 and φ2 the offset will decrease progressively; its maximum value is: V a V V A V V a o s o s o s

Optimization of pipelined ADC architecture for Monolithic Active Pixel Sensors

For CMOS monolithic active pixels sensor readout, we developed two architectures of low power and low signal pipelined analog to digital converter (ADC) which are 5 bit, 25 MS/s pipelined ADC and 4 bit, 50 MS/s double sampling ADC. Both architectures include a non-resetting sample and hold stage to amplify the signal by a factor of 4. Due to the very low level of the incoming signal, this first stage compensates both of the amplifier offset effect and the input common mode voltage dispersion. The traditional pipelined ADC consists of three 1.5 bit sub-ADC and a 2 bit flash. And the double sampling architecture consists of one double channel 2.5 bit stage followed by a 2 bit flash stage. We present the results of prototypes, made of eight ADC channels. A comparative study is done. For the above designs, the full analog part of the converter can be quickly switched to a standby idle mode in less than lus; thus reducing the power dissipation to a ratio better than 1/1000. This fast shutdown is very important for the ILC vertex detector as the total DC power dissipation becomes directly proportional to the low beam duty cycle.