D. Flores

Continuous analytic I-V model for surrounding-gate MOSFETs

We present a continuous analytic current-voltage (I-V) model for cylindrical undoped (lightly doped) surrounding gate (SGT) MOSFETs. It is based on the exact solution of the Poissons equation, and the current continuity equation without the charge-sheet approximation, allowing the inversion charge distribution in the silicon film to be adequately described. It is valid for all the operation regions (linear, saturation, subthreshold) and traces the transition between them without fitting parameters, being ideal for the kernel of SGT MOSFETs compact models. We have demonstrated that the I-V characteristics obtained by this model agree with three-dimensional numerical simulations for all ranges of gate and drain voltages.

Radiation effects in Low Gain Avalanche Detectors after hadron irradiations

Novel silicon detectors with charge gain were designed (Low Gain Avalanche Detectors - LGAD) to be used in particle physics experiments, medical and timing applications. They are based on a n++-p+-p structure where appropriate doping of multiplication layer (p^+) is needed to achieve high fields and impact ionization. Several wafers were processed with different junction parameters resulting in gains of up to 16 at high voltages. In order to study radiation hardness of LGAD, which is one of key requirements for future high energy experiments, several sets of diodes were irradiated with reactor neutrons, 192 MeV pions and 800 MeV protons to the equivalent fluences of up to Φeq=1016 cm−2. Transient Current Technique and charge collection measurements with LHC speed electronics were employed to characterize the detectors. It was found that the gain decreases with irradiation, which was attributed to effective acceptor removal in the multiplication layer. Other important aspects of operation of irradiated detectors such as leakage current and noise in the presence of charge multiplication were also investigated.

Study of novel techniques for reducing self-heating effects in SOI power LDMOS

Abstract Self-heating effects in silicon-on-insulator (SOI) power devices have become a serious problem when the active silicon layer thickness is reduced and buried oxide thickness is increased. Hence, if the temperature of the active region rises, the device electrical characteristics can be seriously modified in steady state and transient modes. In order to alleviate the self heating, two novel techniques which lead to a better heat flow from active silicon layer to silicon substrate through the buried oxide layer in SOI power devices are proposed. No significant changes on device electrical characteristics are expected with the inclusion of the novel techniques. The electro-thermal performance of lateral power devices including the proposed techniques is also presented.

Analysis of hot-carrier degradation in a SOI LDMOS transistor with a steep retrograde drift doping profile

This paper reports the electrical performances of a RF SOI power LDMOS transistor with a retrograde doping profile in the entire drift region. A comparison between retrograde and conventional uniformly doped drift SOI power LDMOS transistors is provide by means of a numerical simulation analysis. The proposed structures exhibit better performances in terms of trapped electron distribution and transconductance degradation with no modification of the breakdown voltage capability. Simulation results show that, at a given bias conditions, the reduction of lateral electric field peak at the silicon surface due to the implementation of the retrograde doping profile accounts for the observed reduction of the hot carrier degradation effect.

Montecarlo simulation of ion implantation into SiC-6H single crystal including channeling effect

Abstract An ion implantation simulator for single crystal 6H-SiC is presented. This simulator uses a Montecarlo method together with either physically based or semiempirical models to calculate the slowing down of the incoming ions in the crystal. Channeling effect, which appears not to be negligible in SiC single crystal for standard ion implantation conditions, arises naturally as a consequence of the crystal structure and valence electrons distribution. The effect of a native oxide, dynamical amorphization and thermal vibration of the lattice atoms, which affect the channeling behavior of the ions, are also included in the simulation. Recent models for electronic stopping are also used. After calibration, the simulation profiles show good agreement with published SIMS profiles.

The thin SOI TGLDMOS transistor: a suitable power structure for low voltage applications

This paper is addressed to the analysis of the trench gate LDMOS transistor (TGLDMOS) in a thin SOI technology and to investigate its suitability for low voltage power applications. The static and dynamic performances have been extensively analyzed by means of numerical simulations and compared with a conventional thin SOI power LDMOS transistor. The specific on-state resistance of the analyzed TGLDMOS structure is lower than that of the LDMOS counterpart, but the structure design has to be optimized to minimize the added contributions to the parasitic capacitances. In this sense, a modified TGLDMOS is also proposed to reduce the gate–drain capacitance and to increase the frequency capability. The expected electrical performance improvements of both TGLDMOS and modified TGLDMOS power transistors corroborate their suitability for 80 V switching and amplifying applications.

Analysis of low-voltage super-junction LDMOS structures on thin-SOI substrates

This paper is addresses the analysis of the super-junction (SJ) concept applied to LDMOS transistors in thin-SOI technology. Extensive numerical simulations have been carried out to investigate their suitability for low-voltage power applications. The static and dynamic performances of different SJLDMOS structures have been studied in comparison with a conventional RESURF LDMOS structure with the same SOI substrate. In order to improve the current-crowding effect at the body/drift region, the inclusion of a trench lateral gate in the SJ structure (TSJLDMOS) is proposed to further decrease the total on-state resistance (Ron) value maintaining the same voltage capability. The increment of the N+ source and N-drift diffusion area overlapping the gate terminal leads to a gate-related capacitance enhancement. Although very low Ron results can be obtained, the capacitance degradation limits the suitability of TSJLDMOS structure in RF power amplifiers.

Reduction of self-heating effect on SOIM devices

Abstract The silicon-on-insulator (SOI) power devices have an inherent self-heating effect, which limits their operation at high current levels. This is a consequence of the very low thermal conductivity of the thick buried oxide layer. A novel solution to reduce the self-heating effect is proposed in this paper, based on silicon-over-insulator-multilayer (SOIM) emerging technology. A significant reduction of the insulator layer thermal resistance is achieved while keeping constant the electrical behaviour of integrated power devices in comparison to the conventional SOI counterparts. The effectiveness of the proposed solution has been corroborated with numerical simulations. Moreover, no additional steps in fabrication processes are required with regard to the conventional SOI technology.

Static and dynamic electrical performances of STI thin-SOI power LDMOS transistors

The benefits of applying the shallow trench isolation (STI) concept to a higher voltage thin-SOI laterally diffused metal oxide semiconductor (LDMOS) (in the range of 80 V) are analysed in this paper by means of 2D technology computer-aided design (TCAD) numerical simulations. The TCAD simulation results allow comparing the electrical performance of the studied STI LDMOS structure with that of a conventional LDMOS in terms of the main static (breakdown voltage (VBR) and specific on-state resistance (RON-sp)) and dynamic (gate–drain capacitance (CGD) and cut-off frequency (fT)) characteristics. Moreover, the impact of the STI length (LSTI) and thickness (TSTI), and the N-drift implantation energy on the electrical characteristics is considered in detail. On the other hand, the STI block helps to move the harmful high electric field further away from the silicon surface, thus minimizing gate–oxide degradation by hot carriers.

Lateral punch-through TVS devices for on-chip protection in low-voltage applications

A novel lateral punch-through TVS (Transient Voltage Suppressor) structure addressed to on-chip protection in very low voltage applications is reported in this paper. Different lateral TVS structures have been studied in order to optimize the electrical performances related with the surge protection capability. Lateral TVS structures with a four-layer doping profile exhibit the best electrical performances, as in the case of vertical TVS devices. The dependence of the basic electrical characteristics on the technological and geometrical parameters is also analysed. Finally, the electrical performances of lateral TVS structures are compared with those of vertical punch-through TVS devices and conventional Zener diodes, being the leakage current level reduced two orders of magnitude in the case of the lateral architecture. Lateral TVS structures exhibits similar performance than vertical counterparts with the advantage of easiest on-chip integration.