D. Gascon

Front End ASIC design for SiPM readout

A Front End ASIC for the readout of Silicon Photo-Multipliers is presented with the following features: wide dynamic range, high speed, multi channel, low input impedance current preamplifier, low power (7mW per channel), DC coupled input with common mode voltage control and separated timing and charge signal output. A detailed description of the SiPM modeling and parameter extraction is also included allowing the emulation of the signal generated by different commercial devices in the design simulation stage. Current prototype is the first step for a more complex mixed signal design including more channels, analog processing and digital outputs, thus reducing power consumption and increasing integration. This prototype includes basic blocks for 3 channels with: preamplifier with two separate signal paths and fast current discriminator with digital output.

FlexToT - Current mode ASIC for readout of common cathode SiPM arrays

A front end application specific integrated circuit (ASIC) for the readout of common cathode Silicon Photo-Multipliers arrays is presented with the following features: wide dynamic range, high speed, multi channel, low input impedance current amplifier, low power (≈10mW per channel), common cathode connection, directly coupled input with common mode voltage control and separated timing and charge signal output.A 16 channel prototype with 16 independent outputs for energy and pile-up detection and a single fast timing output is described. The low jitter current mode processing together with a configurable differential current mode logic (CML) output provides a timing signal suitable for Time of Flight (TOF) applications, such as TOF-PET (Positron Emission Tomography). Each channel delivers a digital output of a Time Over Threshold (TOT) type with a pulse width proportional to peak current (charge) input. The current mode input stage features a novel double feedback; a low speed feedback loop keeps input node voltage constant while a higher speed feedback loop keeps input impedance low. Dedicated circuitry allows SiPM high over-voltage operation, thus maximizing Photon Detection Efficiency (PDE) and timing resolution. Design was submitted in June 2012 in Austria Microsystems (AMS) 0.35 μm HBT BiCMOS technology and is under test.

Study of multianode photomultipliers for the electromagnetic calorimeter preshower read out of the lhcb experiment

Abstract The L hc b experiment will study the CP symmetry violation in the system of the beauty particles. The detector is a 20-m-long spectrometer, to be installed on the proton–proton collider L hc . Of major importance for the level 0 trigger is the preshower of the electromagnetic calorimeter designed to discriminate between electrons, hadrons and photons. The preshower cells consist of a two-radiation-length lead sheet located between two plastic scintillator planes. The scintillation light is extracted with wavelength-shifting fibres. The best candidates to read out the light of the 6000 detector cells are multianode photomultipliers. The HAMAMATSU photomultiplier R5900-00-M64 has been studied and its responses in terms of gain, linearity, uniformity within and between the anodes and cross-talk between the channels are addressed in this document.

Wideband (500 MHz) 16 bit dynamic range current mode PreAmplifier for the CTA cameras (PACTA)

A wideband current mode preamplifier with 16 bits dynamic range (DR) is presented. It has been designed for the cameras of the Cherenkov Telescope Array (CTA). A novel current division scheme at the very front end part of the circuit splits the input current into two scaled currents which are connected to independent current mirrors. The mirror of the high gain path comprises a saturation control circuit for accurate current division. Measurement results of an ASIC designed in Austriamicrosystems 0.35 μm SiGe technology are presented: 500 MHz BW, 16 bits DR, 10 pA/sqrt(Hz) input referred noise current and relative linearity error below 3%.

Low noise front end ICECAL ASIC for the upgrade of the LHCb calorimeter

A fully differential ASIC with cooled input termination is presented as a solution for the Upgrade of the Calorimeter front end electronics. The LHCb experiment needs to increase about ten times the integrated luminosity in order to study new physics. The increase in signal has to be compensated reducing the gain of the photomultipliers which implies stringent noise requirements. The proposed solution offers an active termination at the input and avoids the noise originated by the use of a resistor. The circuit is based on a two interleaved channel with a first amplifier stage, a switched integrator, and a Track-and-Hold. Two prototypes have been implemented and tested in SiGe BiCMOS 0.35um technology.

Readout electronics for low dark count pixel detectors based on Geiger mode avalanche photodiodes fabricated in conventional CMOS technologies for future linear colliders

High sensitivity and excellent timing accuracy of the Geiger mode avalanche photodiodes make them ideal sensors as pixel detectors for particle tracking in high energy physics experiments to be performed in future linear colliders. Nevertheless, it is well known that these sensors suffer from dark counts and afterpulsing noise, which induce false hits (indistinguishable from event detection) as well as an increase in the necessary area of the readout system. In this work, we present a comparison between APDs fabricated in a high voltage 0.35 mm and a high integration 0.13 mm commercially available CMOS technologies that has been performed to determine which of them best fits the particle collider requirements. In addition, a readout circuit that allows low noise operation is introduced. Experimental characterization of the proposed pixel is also presented in this work.

High voltage vs. high integration: a comparison between CMOS technologies for SPAD cameras

In the last years the fabrication of SPAD cameras has become one of the main fields of interest in 3-D imaging and bioapplications. In this paper we present the comparison between two standard CMOS technologies to fabricate SPADs cameras. The two technologies used in the comparison are a high voltage 0.35μm technology from AMS and a high integration 130nm technology from STM. The advantage of using a standard CMOS technology among a dedicated is the possibility of integrating the control/reading electronics into the same die. Neither of the processes is optimized for optical applications, and no post-processing has been applied to improve the features. The technologies have been selected due to the different integration density, and different intrinsic process parameters with similar cost. Comparison has been done by fabricating several structures in both technologies which allow analyzing sensibility, noise, and time response. Experimental results show that the high voltage technology has a lower level of dark counts than the 130nm. Instead, the high integration technology has a shorter quenching time, 1.5ns, which reduces the afterpulsing events to a negligible level. In optical applications it is important to have a high integration of the camera reducing the pitch of the pixel, while noise effects can be corrected in post-processing. For low frequency events, such as high energetic particle tracking, the noise frequency has to be lower, but it is also required a high fill factor. Depending on the specific application this analysis allows to opt for the most suitable technology.

Readout electronics for low dark count Geiger mode avalanche photodiodes fabricated in conventional HV-CMOS technologies for future linear colliders

This work presents low noise readout circuits for silicon pixel detectors based on Geiger mode avalanche photodiodes. Geiger mode avalanche photodiodes offer a high intrinsic gain as well as an excellent timing accuracy. In addition, they can be compatible with standard CMOS technologies. However, they suffer from a high intrinsic noise, which induces false counts indistinguishable from real events and represents an increase of the readout electronics area to store the false counts. We have developed new front-end electronic circuitry for Geiger mode avalanche photodiodes in a conventional 0.35 μm HV-CMOS technology based on a gated mode of operation that allows low noise operation. The performance of the pixel detector is triggered and synchronized with the particle beam thanks to the gated acquisition. The circuits allow low reverse bias overvoltage operation which also improves the noise figures. Experimental characterization of the fabricated front-end circuit is presented in this work.

NectarCAM : a camera for the medium size telescopes of the Cherenkov Telescope Array

NectarCAM is a camera proposed for the medium-sized telescopes of the Cherenkov Telescope Array (CTA) covering the central energy range of ~100 GeV to ~30 TeV. It has a modular design and is based on the NECTAr chip, at the heart of which is a GHz sampling Switched Capacitor Array and a 12-bit Analog to Digital converter. The camera will be equipped with 265 7-photomultiplier modules, covering a field of view of 8 degrees. Each module includes the photomultiplier bases, high voltage supply, pre-amplifier, trigger, readout and Ethernet transceiver. The recorded events last between a few nanoseconds and tens of nanoseconds. The camera trigger will be flexible so as to minimize the read-out dead-time of the NECTAr chips. NectarCAM is designed to sustain a data rate of more than 4 kHz with less than 5\% dead time. The camera concept, the design and tests of the various subcomponents and results of thermal and electrical prototypes are presented. The design includes the mechanical structure, cooling of the electronics, read-out, clock distribution, slow control, data-acquisition, triggering, monitoring and services.

Low noise front end ASIC with current mode active cooled termination for the Upgrade of the LHCb Calorimeter

An integrated circuit for the Upgrade of the LHCb Calorimeter front end electronics is presented. The circuit is based on a current mode input stage followed by two fully differential interleaved channels with a switched integrator and a track and hold. The input stage employs a novel electronically cooled input termination scheme to achieve the stringent noise requirements. Compared to previous designs, its novelty relies in the use of two current feedback loops to decrease and control the input impedance of a common base stage. Two prototypes in AMS SiGe BiCMOS 0.35um technology have been designed and tested. Key measurements have been performed. Reflection coefficient is smaller than 0.5% for the full dynamic range, which is 12 bits. Relative linearity error is below 1 %. Output noise is about 1 LSB after aplying correlated double sampling.