D. M. Akbar Hussain

I/O standard based thermal/energy efficient green communication for Wi-Fi protected access on FPGA

In this paper, we analyzed how does life and reliability of an integrated circuit is affected when it is operated in different regions under different temperatures. We have taken Fibonacci generator as our target circuit and LVCMOS as I/O standards. WPA and WPA2 (Wi-Fi Protected Access) key can be generated with Fibonacci generator. Here, thermal efficient green Fibonacci Generator is used to generate key for Wi-Fi Protected Access in order to make green communication possible under different room temperature. By analysis it is observed that at standard normal temperature (21°C), LVCMOS12 have 24%, 17.3% and 95.53% less junction temperature than LVCMOS25 at operating frequencies of 1 GHz, 10 GHz, and 100 GHz respectively, while at 1 THz, the junction temperature becomes 125°C, which causes unreliability for circuit and device may not operate at that frequency. For worlds highest temperature (56.7°C), we achieve 0.97% and 8.29% reduction in junction temperature at 1 GHz and 10 GHz operating frequencies respectively. This design is implemented in verilog on virtex-6 FGPA. Usually for functioning of a device, the junction temperature is below 125°C.

LQG controller design for pitch regulated variable speed wind turbine

Variable speed wind turbine is a complex and nonlinear system, a sophisticated control is required to meet the challenges posed by these systems. This paper is presenting a pitch regulation strategy based on LQG (Linear Quadratic Gaussian) to regulate turbine at its rated power and to reject the effect of disturbance acting on its rotor blades by wind. CART2 (Control Advanced Research Turbine) linear model is produced/generated by FAST (Fatigue, Aerodynamics, Structures and Turbulence) code to test its simulation on MATLAB/Simulink and various results are compared. The designed controller provide better disturbance rejection performance as compared to PID controller.

Wireless Networks, Information Processing and Systems

Keynote Speech: Role of PCSIR in Industrial Development of Pakistan -- Keynote Speech: Computer Vision: Object Recognition and Scene Interpretation -- Electronic Automatic Gear Shifting System for a Motorcycle -- Segmentation of Arabic Text into Characters for Recognition -- Improved Texture Description with Features Based on Fourier Transform -- Optimization of Projections for Parallel-Ray Transmission Tomography Using Genetic Algorithm -- Seasonal to Inter-annual Climate Prediction Using Data Mining KNN Technique -- Application of a Proposed Efficient Smoothing Algorithm on Directional Vectors for Isolated Handwritten Characters -- Architecture Based Reliability and Testing Estimation for Mobile Applications -- A Framework to Achieve Reverse Channel Multicast in IEEE 802.16 Based Wireless Broadband Networks for Interoperability with IP Networks -- A Dynamical System and Neural Network Perspective of Karachi Stock Exchange -- A Novel Approach to Non Coherent UWB Reception -- Load Balancing in EAMC to Integrate Heterogeneous Wireless Systems -- A Speech Recognition System for Urdu Language -- The Future of Satellite Communications in Pakistan -- The Small World of Web Network Graphs -- Application of Color Segmentation Using Online Learning for Target Tracking -- Iterative Learning Fuzzy Gain Scheduler -- Comparative Analysis of Mobile IP and HAWAII -- Video Transport over Heterogeneous Networks Using SCTP and DCCP -- Implementing Constructivist Pedagogical Model in Dynamic Distance Learning Framework -- Effect of Schedule Compression on Project Effort in COCOMO II Model for Highly Compressed Schedule Ratings -- The Concept of Bio-fitness in Bio-inspired Computational Metaphor Abstraction -- Analysis of MANET Routing Protocols under TCP Vegas with Mobility Consideration -- CMMI and OPM3: Are They Compatible? -- Impact of Cluster Size on Efficient LUT-FPGA Architecture for Best Area and Delay Trade-Off -- Effects of Social Status on Foetal Growth Using Obstetric Ultrasonography – A Biometric Approach -- Bioinformatics Awareness System for Skin Diseases Using Stem Cells Therapy in the Perspective of eHealth -- How to Build an Open Source Render Farm Based on Desktop Grid Computing -- Implementation Challenges for Nastaliq Character Recognition -- Enhancing Business Decisions with Neurofuzzy Technology -- A System Design for a Telemedicine Health Care System -- Performance Analysis of PDC-OCDMA System with APD Mismatch -- Blocking Probabilities in WDM Switching Networks Using Overflow Analysis Method -- Design and Implementation of a Selective Harmonic Elimination SPWM Strategy-Based Inverter -- Case Study: Investigating the Performance of Interactive Multiple Motion Model Algorithm for a Crossing Target Scenario -- A Novel Approach for the Control of Dual-Active Bridge DC-DC Converter -- Importance of Data Center Philosophy, Architecture and Its Technologies -- Keynote Address: Is It Right and Is It Legal? -- Practical Optimal Caching Using Multiple Virtual Caches in Multiple Query Optimization -- A Design and Chronological Survey of Decision Feedback Equalizer for Single Carrier Transmission Compared with OFDM -- Speaker Verification Based on Information Theoretic Vector Quantization -- Detecting Trojans Using Data Mining Techniques -- Enabling MPSoC Design Space Exploration on FPGAs -- Range Based Real Time Localization in Wireless Sensor Networks -- PrISM: Automatic Detection and Prevention from Cyber Attacks -- A Pretty Safe Strategy for Analyzing Discrete Security Assessment Framework in Wireless Sensor Networks -- Renewable Energy for Managing Energy Crisis in Pakistan.

SSTL I/O Standard based environment friendly energyl efficient ROM design on FPGA

Stub Series Terminated Logic (SSTL) is an Input/output standard. It is used to match the impedance of line, port and device of our design under consideration. Therefore, selection of energy efficient SSTL I/O standard among available different class of SSTL logic family in FPGA, plays a vital role to achieve energy efficiency in design under test (DUT). Here, DUT is ROM. ROM is an integral part of processor. Therefore, energy efficient design of RAM is a building block of energy efficient processor. We are using Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator. We are operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use. When there is no demand of peak performance, then we can save 74.5% clock power, 75% signal power, and 30.83% I/O power by operating our device with 1GHz frequency in place of 4GHz. There is no change in clock power and signal power but SSTL2_H_DCI having 80.24% 83.38% 62.92% and 76.52% and 83.03% more I/O power consumption with respect to SSTL2_I, SST18_I, SSTL2_I_DCI, SSTL2_II, and SSTL15 respectively at 3.3GHz.

Investigation of Key-Player Problem in Terrorist Networks Using Bayes Conditional Probability

In Social Network Analysis (SNA) it is quite conventional to employ graph theory concepts for example cut-points and cut-sets or measuring node centralities like betweenness, degree and closeness to highlight important actors in the network. However, it is also believed that most of these measures alone are inadequate for investigating terrorist/covert networks. In this paper we compute posterior probability using Bayes conditional probability theorem to compute each nodes positional probability to see how probable/likely that the node is a key player. Obviously, larger the probability value higher is the chances that the node is a key actor, the system after words using the computed probability can select an arbitrary number of nodes for elimination to make the network non-functional or severely destroying its capability. We know that that network fragmentation in its simplest form is a count of the number of components, more the number of counts larger is the fragmentation. The reason of calling it simple is because it does not include many aspects of the network for example structure etc. Borgatti has provided a similar measure which does includes the shape and internal structure of the components and high light the important actors in the network. Our computational procedure provides very similar results in highlighting the key player problem. We simulated our computational model through various random networks and we also applied it to the David Krackhardt’s kite network and to 9-11 hijackers network to bench mark our results. It shows that conceptually this framework of evaluation can be used to highlight the key players in terrorist/covert cells.

DAC to mitigate the effect of periodic disturbances on drive train using collective pitch for variable speed wind turbine

DAC is a linear control technique used to mitigate the effect of disturbance on the plant. It is a superposition of full state feedback and disturbance feedback. This paper presents a control technique based on Disturbance Accommodation Control (DAC) to reduce fatigue on drive train generated by wind which is combination of step and periodic disturbances (generated by wind shear and tower shadow) of the turbine for above rated wind speed (Region III). We have presented a wind modeling for wind shear and tower shadow effect for the wind turbine control simulation and also developed a control scheme to mitigate the effect of 3p flicker on drive train. 5MW wind turbine of the National Renewable Laboratories (NREL) is used as research object and results are simulated in MATLAB/Simulink. We designed the controller based on linearized model of the wind turbine generated for above rated wind speed and then tested its performance on the nonlinear model of wind turbine. We have shown a comparison of the results for proportional-integral(PI) and proposed DAC controller tested on nonlinear model of wind turbine. Result shows that our proposed controller shows better mitigation of flicker generated due to 3p effect by using collective pitch control as compared to PI with tower and actuator dynamics.

DAC with LQR control design for pitch regulated variable speed wind turbine

Disturbance Accommodation Control (DAC) is used to model and simulate a system with known disturbance waveform. This paper presents a control scheme to mitigate the effect of disturbances by using collective pitch control for the above-rated wind speed (Region III) for a variable speed wind turbine. We have used Linear Quadratic Regulator (LQR) to obtain full state feedback gain, disturbance feedback gain is calculated independently and then estimator gain is achieved by pole-placement technique in the DAC augmented plant model. The reduced order model (two-mass model) of wind turbine is used and 5MW National Renewable Energy Laboratory (NREL) wind turbine is used in this research. We have shown comparison of results relating to pitch angle, drive train torsion and generator speed obtained by a PID controller and DAC. Simulations are performed in MATLAB/Simulink. The results are compared with PID controller for a step wind and also for turbulent wind disturbance. DAC method shows better regulation in output power and less fatigue of drive train in the presence of pitch actuator limits. Proposed controller tested on wind turbine shows better robustness and stability as compared to PID. The paper describes practical experiences to develop a new DC power plant controller user interface based on human-centered design ideas.

GTL based Internet of Things enable processor specific RAM design on 65nm FPGA

In this work, we Energy Efficient Internet of Things (IoTs) Enable RAM is presented. In order to make it energy efficient, used Gunning Transceiver Logic (GTL) IO Standard and Gunning Transceiver Logic Plus (GTLP). We used the 4 different members of GTL and GTLP IO standards family and searched the most energy efficient among them. We observed that when we use 3.6 GHz operating frequency, there is 90.2% reduction in I/O power when we used GTL instead of GTLP_DCI. We have inserted a 128-bit IP address in RAM to make internet of things enable RAM. Finally, we operated our IOTs Enable RAM with different operating frequency of I3, I5, I7, Moto-E and Moto-X.

Harmonie detection at initialization with Kaiman filter

Most power electronic equipment these days generate harmonic disturbances, these devices hold nonlinear voltage/current characteristic. The harmonics generated can potentially be harmful to the consumer supply. Typically, filters are integrated at the power source or utility location to filter out the affect of harmonics on the supply. For the detection of these harmonics various techniques are available and one of that technique is the Kaiman filter. In this paper we investigate that what are the consequences when harmonic detection system based on Kalman Filtering is initialized/switched on and at the same time harmonic/s are introduced in the system.

LVTTL based energy efficient watermark generator design and implementation on FPGA

In print image, a watermark is an identifiable pattern which when viewed by reflected light seems to have different shades of lightness. In digital image, a watermark is a pattern, which is embedded in image to ensure the security and quality of an image. In this work, our main concern is design of energy efficient Watermark Generator (WMG) for video frame in order to gain extended life of the battery in the camera because the WMG is embedded into camera. We have assumed that target device is operating under five different frequencies and five different drive strength values. Low voltage Transistor-transistor logic (LVTTL) IO standard is used in this design to make it power optimized. This design is implemented on Kintex-7 FPGA, Device XC7K70T and -3 speed grades. When we are scaling the device operating frequency from 100GHz to 5GHz, there is 94.93% saving in total power of the watermark generator. It is also observed that when we scale down the drive strength from 24mA to 4mA, we achieve 3-4% saving in IO power of the target device.