D. Moraes

Development of the CARIOCA front-end chip for the LHCb muon detector

Abstract CERN and Rio Current-mode Amplifier is an amplifier–shaper–discriminator chip, developed in 0.25 μm CMOS radiation tolerant technology for the readout of the LHCb muon wire chambers. This paper presents the design and test of three prototype chips, including positive and negative pre-amplifier, differential shaper, differential discriminator and LVDS driver circuits.

A Time-Based Front End Readout System for PET & CT

In the framework of the European FP6s BioCare project, we develop a novel, time-based, photo-detector readout technique to increase sensitivity and timing precision for molecular imaging in PET and CT. The project aims to employ Avalanche Photo Diode (APD) arrays with state of the art, high speed, front end amplifiers and discrimination circuits developed for the Large Hadron Collider (LHC) physics program at CERN, suitable to detect and process photons in a combined one-unit PET/CT detection head. In the so-called time-based approach our efforts focus on the systems timing performance with sub-nanosecond time-jitter and -walk, and yet also provide information on photon energy without resorting to analog to digital conversion. The bandwidth of the electronic circuitry is compatible with the scintillators intrinsic light response (e.g. les40ns in LSO) and hence allows high rate CT operation in single-photon counting mode. Based on commercial LSO crystals and Hamamatsu S8550 APD arrays, we show the system performance in terms of timing- and energy resolution as well as its rate behavior (SPICE, simulating a high intensity X-ray beam). If proven viable, this technique may lead to the construction of a compact, radiation tolerant, and cost effective PET/CT detection head in one unit.

Hydrogenated Amorphous Silicon Sensor Deposited on Integrated Circuit for Radiation Detection

Radiation detectors based on the deposition of a 10 to 30 mum thick hydrogenated amorphous silicon (a-Si:H) sensor directly on top of integrated circuits have been developed. The performance of this detector technology has been assessed for the first time in the context of particle detectors. Three different circuits were designed in a quarter micron CMOS technology for these studies. The so-called TFA (Thin-Film on ASIC) detectors obtained after deposition of a-Si:H sensors on the developed circuits are presented. High internal electric fields (104 to 105 V/cm) can be built in the a-Si:H sensor and overcome the low mobility of electrons and holes in this amorphous material. However, the deposited sensors leakage current at such fields turns out to be an important parameter which limits the performance of a TFA detector. Its detailed study is presented as well as the detectors pixel segmentation. Signal induction by generated free carrier motion in the a-Si:H sensor has been characterized using a 660 nm pulsed laser. Results obtained with a TFA detector based on an ASIC integrating 5 ns peaking time pre-amplifiers are presented. Direct detection of 10 to 50 keV electrons and 5.9 keV X-rays with the detectors are then shown to understand the potential and the limitations of this technology for radiation detection.

Guard ring elimination in CdTe and CdZnTe detectors

CdTe and CdZnTe deliver good energy resolution and stopping power in a room temperature solid state detector. Currently, these materials are becoming more available and larger detectors are being constructed by tiling many single crystal modules together. However, CdTe and CdZnTe remain expensive and it is therefore desirable to make use of as much of the crystal as possible and to tile the individual crystals closely with little or no dead space. Reducing surface current on these crystals without the use of guard rings could allow pixel maps to be extended to the edge of the crystal, thus making more effective use of the material and allowing tiling with less dead space. We have therefore developed a method of passivating the surface current in single crystal CdTe and CdZnTe detectors. Using this passivation method we have constructed a CdTe detector with 256 pixels which extend all the way to the edge of the crystal. To validate our results, we have also constructed a testing device, based on spring loaded gold plated pins, which can non-destructively test the current in each pixel of such a detector. Using this testing device, we have compared the dark current of edge pixels before and after our passivation process and see a significant reduction in surface current after passivation. The elimination of guard rings along with our implementation of a backplane readout solution allows this detector module to be tiled with dead space close that of the pixel septa.

Front-end electronics for the readout of CdZnTe sensors

The CERN/spl I.bar/DxCTA is a front-end ASIC optimized for the readout of CdZnTe sensors. The chip is implemented in 0.25 /spl mu/m CMOS technology. The circuit consists of 128 channels equipped with a transimpedance amplifier followed by a gain-shaper stage with 20 ns peaking time and two discriminators, allowing two threshold settings. Each discriminator includes a 5-bit trim DAC and is followed by an 18-bit static ripple-counter. The channel architecture is optimized for the detector characteristics in order to achieve the best energy resolution at counting rates of up to 5 M counts/second. Complete evaluation of the circuit is presented using electronic pulses and CdZnTe pixel detectors.

Image Sensors Based on Thin-film on CMOS Technology: Additional Leakage Currents due to Vertical Integration of the a-Si:H Diodes

Note: IMT-NE Number: 437 Reference PV-LAB-CONF-2006-010 Record created on 2009-02-10, modified on 2017-05-10

Vertically Integrated Amorphous Silicon Particle Sensors

Note: IMT-NE Number: 388 Reference PV-LAB-CONF-2004-018 Record created on 2009-02-10, modified on 2017-05-10

Front-end counting mode electronics for CdZnTe sensor readout

The development of a front-end circuit optimized for CdZnTe detector readout, implemented in 0.25 /spl mu/m CMOS technology, is reported. The ASIC comprises 17 channels of a charge sensitive amplifier with an active feedback, followed by a gain-shaper stage and a discriminator with a 5 bit fine-tune DAC. The signal from the discriminator is sensed by a 25 ns mono-stable circuit and an 18-bit static ripple-counter. The channel architecture is optimized for the detector characteristics in order to achieve the best energy resolution at a maximum counting rate of 2 million counts/second. The amplifier shows a linear sensitivity of 24 mV/fC with 50 ns peaking time and an equivalent noise charge of about 650 e/sup -/, for a detector capacitance of 10 pF. When connected to a 3/spl times/3/spl times/7 mm/sup 3/ CdZnTe detector the amplifier gain is about 8 mV/keV with a noise around 3.6 keV.

Development of a New Photo‐detector Readout Technique for PET and CT

In the framework of the European FP6s BioCare project, we develop a novel photo‐detector readout technique to increase sensitivity and timing precision for molecular imaging in PET and CT. Within the Projects work packages, the CERN‐BioCare group focuses on the development of a PET detection head suitable to process data from both PET and CT operation in one unit. The detector module consists of a LSO matrix coupled to an APD array. The signal is processed by fast and low noise readout electronics recently developed for experiments at the Large Hadron Collider (LHC) at CERN. The functioning of this time based system is presented as well as its performances in terms of energy resolution.

Radiation hard amorphous silicon particle sensors

Note: IMT-NE Number: 409 Reference PV-LAB-CONF-2005-016 Record created on 2009-02-10, modified on 2017-05-10