D.S. Smith

Design, production, and reliability of the new ATLAS pixel opto-boards

New fiber optical transceivers, opto-boards, were designed and produced to replace the first generation opto-boards installed in the ATLAS pixel detector and for the new pixel layer, the insertable barrel layer (IBL). Each opto-board contains one 12-channel PIN array and two 12-channel VCSEL arrays along with associated receiver and driver ASICs. The new opto-board design benefits from the production and operational experience of the first generation opto-boards and contains several improvements. The new opto-boards have been successfully installed. Additionally, a set of the new opto-boards have been subjected to an accelerated lifetime experiment at 85 C and 85% relative humidity for over 1,000 hours. No failures were observed. We are cautiously optimistic that the new opto-boards will survive until the shutdown for the detector upgrade for the high-luminosity Large Hadron Collider (HL-LHC).

The BaBar LST detector high voltage system: design and implementation

In 2004, the first two sextants of the new limited streamer tube (LST) detector were installed in the BaBar experiment to replace the ageing resistive plate chambers (RPCs) as active detectors for the BaBar instrumented flux return (IFR) muon system. Each streamer tube of the new detector consists of 8 cells. The cell walls are coated with graphite paint and a 100 /spl mu/m wire forms the anode. These wires are coupled in pairs inside the tubes resulting in 4 independent two-cell segments per LST. High voltage (HV) is applied to the 4 segments through a custom connector that also provides the decoupling capacitor to pick up the detector signals from the anode wires. The BaBar LST detector is operated at 5.5 kV. The high voltage system for the LST detector was designed and built at the Ohio State University (OSU HVPS). Each of the 25 supplies built for BaBar provides 80 output channels with individual current monitoring and overcurrent protection. For each group of 20 channels the HV can be adjusted between 0 and 6 kV. A 4-fold fan-out is integrated in the power supplies to provide a total of 320 outputs. The power supplies are controlled through built-in CANbus and Ethernet (TCP/IP) interfaces. In this presentation we will discuss the design and novel features of the OSU HVPS system and its integration into the BaBar EPICS detector control framework. Experience with the supplies operation during the LST extensive quality control program and their performance during the initial data taking period will be discussed.

Development of the hitbus chip platform for the ATLAS DBM detector at CERN

The Large Hadron Collider at CERN is presently in a two year shutdown for upgrades. Among the upgrades include insertion of a new detector in the ATLAS experiment called the Diamond Beam Monitor. Included in the DBM is a radiation hard application specific integrated circuit, the Hitbus chip platform, to allow the DBM to trigger its own readout. Intellectual property (IP) from several collaborating institutes were gathered and combined with new custom blocks to create the platform. We present the design, verification, performance, experiences from the collaborative process, and results from an irradiation with 24 GeV protons to 115 Mrad.

Radiation-hard optical link for SLHC

We study the feasibility of fabricating an optical link for the SLHC ATLAS silicon tracker based on the current pixel optical link architecture. The electrical signals between the current pixel modules and the optical modules are transmitted via micro-twisted cables. The optical signals between the optical modules and the data acquisition system are transmitted via rad-hard SIMM fibres spliced to rad-tolerant GRIN fibres. The link has several nice features. We have measured the bandwidths of the micro twisted-pair cables to be 1 Gb/s and the fusion spliced fibre ribbon to be 2 Gb/s. We have irradiated PIN and VCSEL arrays with 24 GeV protons and find the arrays survive to the SLHC dosage. We have also demonstrated the feasibility of fabricating a novel opto-pack for housing VCSEL and PIN arrays with BeO as the substrate.

10 Gb/s Radiation-Hard Parallel Optical Engine

We have designed and fabricated a compact array-based optical engine for transmitting data at 10 Gb/s. The device consists of a 4-channel ASIC driving a VCSEL (Vertical Cavity Surface Emitting Laser) array in an optical package. The ASIC is designed using only core transistors in a 65 nm CMOS process to enhance the radiation-hardness. The ASIC contains an 8-bit DAC to control the bias and modulation currents of the individual channels in the VCSEL array. The DAC settings are stored in SEU (single event upset) tolerant registers. Several devices were irradiated with 24 GeV/c protons and the performance of the devices is satisfactory after the irradiation.

High-Speed/Radiation-Hard Optical Engine for HL-LHC

We have designed and fabricated a compact array-based optical engine for transmitting data at 10 Gb/s. The device consists of a 4-channel ASIC driving a VCSEL (Vertical Cavity Surface Emitting Laser) array in an optical package. The ASIC is designed using only core transistors in a 65 nm CMOS process to enhance the radiation-hardness. The ASIC contains an 8-bit DAC to control the bias and modulation currents of the individual channels in the VCSEL array. The DAC settings are stored in SEU (single event upset) tolerant registers. Several devices were irradiated with 24 GeV/c protons and the performance of the devices is satisfactory after the irradiation.

Radiation-hard/high-speed array-based optical engine

We have designed and fabricated a compact array-based optical engine for transmitting data at 10 Gb/s. The device consists of a 4-channel ASIC driving a VCSEL (Vertical Cavity Surface Emitting Laser) array in an optical package. The ASIC is designed using only core transistors in a 65 nm CMOS process to enhance the radiation-hardness. The ASIC contains an 8-bit DAC to control the bias and modulation currents of the individual channels in the VCSEL array. The DAC settings are stored in SEU (single event upset) tolerant registers. Several devices were irradiated with 24 GeV/c protons and the performance of the devices is satisfactory after the irradiation.

10 Gb/s radiation-hard VCSEL array driver

We present an R&D program to develop an ASIC that contains a 12-channel VCSEL (Vertical Cavity Surface Emitting Laser) array driver operating at 10 Gb/s per channel, yielding an aggregated bandwidth of 120 Gb/s. The design of the 10 Gb/s array driver ASIC is based on a prototype ASIC for driving a VCSEL array at 5 Gb/s. We will briefly describe the design of the 5 Gb/s ASIC that was fabricated in a 130 nm CMOS process. Two ASICs were irradiated with 800 MeV protons to a dose of 0.92×1015 1-MeV neq/cm2 and remain operational. For the 10 Gb/s VCSEL array driver ASIC, we have submitted for fabrication a four-channel test chip using a 65 nm CMOS process. The circuit design together with the result from a simulation of the extracted layout with parasitic capacitance and inductance will be presented.

Radiation-hard/high-speed parallel optical links

We have designed an ASIC for use in a parallel optical engine for a new layer of the ATLAS pixel detector in the initial phase of the LHC luminosity upgrade. The ASIC is a 12channel VCSEL (Vertical Cavity Surface Emitting Laser) array driver capable of operating up to 5 Gb/s per channel. The ASIC is designed using a 130 nm CMOS process to enhance the radiation-hardness. A scheme for redundancy has also been implemented to allow bypassing of a broken VCSEL. The ASIC also contains a power-on reset circuit that sets the ASIC to a default configuration with no signal steering. In addition, the bias and modulation currents of the individual channels are programmable. We have received the ASIC and the performance up to 5 Gb/s is satisfactory. Furthermore, we are able to program the bias and modulation currents and to bypass a broken VCSEL channel. We are currently upgrading our design to allow operation at 10 Gb/s per channel yielding an aggregated bandwidth of 120 Gb/s. Some preliminary results of the design will be presented.

Radiation-hard/high-speed parallel optical engine

We have designed an ASIC for use in a parallel optical engine for a new layer of the ATLAS pixel detector in the initial phase of the LHC luminosity upgrade. The ASIC is a 12-channel VCSEL (Vertical Cavity Surface Emitting Laser) array driver capable of operating up to 5 Gb/s per channel. The ASIC is designed using a 130 nm CMOS process to enhance the radiation-hardness. A scheme for redundancy has also been implemented to allow bypassing of a broken VCSEL. The ASIC also contains a power-on reset circuit that sets the ASIC to a default configuration with no signal steering. In addition, the bias and modulation currents of the individual channels are programmable. We have received the ASIC and the performance up to 5 Gb/s is satisfactory. Furthermore, we are able to program the bias and modulation currents and to bypass a broken VCSEL channel. We are currently upgrading our design to allow operation at 10 Gb/s per channel yielding an aggregated bandwidth of 120 Gb/s. Some preliminary results of the design will be presented.