Da Wei Chang

A Portable Wireless Online Closed-Loop Seizure Controller in Freely Moving Rats

A considerable portion of epilepsy cannot be well treated by available therapies nowadays. Brain stimulation with closed-loop seizure control has recently been proposed as an innovative and effective alternative. A portable wireless online closed-loop seizure controller in freely moving rats was developed and shown with several aspects of advantages, including the following: 1) high accuracy of real-time seizure detection (92-99% during wake-sleep states); 2) low cost; and 3) low power consumption. The seizure detection latency was not greater than 0.6 s after seizure onset. A wireless communication feature also provided flexibility for subjects freeing from the hassle of wires. The observation showed that the stimulation elicited no abnormal behavior and had no sleep interruption to the subjects. The experiment data supported the functional possibility of a real-time closed-loop seizure controller.

ROSE: A Novel Flash Translation Layer for NAND Flash Memory Based on Hybrid Address Translation

A Flash Translation Layer (FTL) provides a block device interface on top of flash memory to support disk-based file systems. Due to the erase-before-write feature of flash memory, an FTL usually performs out-of-place updates and uses a cleaning procedure to reclaim stale data. A hybrid address translation (HAT)-based FTL combines coarse-grained and fine-grained address translation to achieve good performance while keeping the size of the mapping information small. In this paper, we propose a new HAT-based FTL, called ROSE, which includes three novel techniques for reducing the cleaning cost. First, it reduces high-cost reclamation by preventing data in an entire-block sequential write from being placed into multiple physical blocks while eliminating the cleaning cost resulting from mispredicting random or semisequential writes as sequential ones. Second, it uses a merge-aware cleaning policy that considers both the block age and the merge cost in a HAT-based FTL for improving the cleaning efficiency. Third, it delays the erasure of obsolete blocks and reuses their free pages for buffering more writes. Simulation results show that the proposed FTL outperforms existing HAT-based FTLs in terms of both cleaning cost and flash write time by up to 47 times and 1.6 times, respectively.

Closed-loop seizure control on epileptic rat models

In this paper numerous alternative treatments in addition to pharmacological therapy are proposed for their use in epileptic patients. Epileptic animal models can play a crucial role in the performance evaluation of new therapeutic techniques. The objective of this research is to first develop various epileptic rat models; second, develop a portable wireless closed-loop seizure controller including on-line seizure detection and real-time electrical stimulation for seizure elimination; and third, apply the developed seizure controller to the animal models to perform on-line seizure elimination. The closed-loop seizure controller was applied to three Long-Evans rats with spontaneous spike-wave discharges (non-convulsive) and three Long-Evans rats with epileptiform activities induced by pentylenetetrazol (PTZ) injection (convulsive) for evaluation. The seizure detection accuracy is greater than 92% (up to 99%), and averaged seizure detection latency is less than 0.6 s for both spontaneous non-convulsive and PTZ-induced convulsive seizures. The average false stimulation rate is 3.1%. Near 30% of PTZ-induced convulsive seizures need more than two times of 0.5 s electrical stimulation for suppression and 90% of the non-convulsive seizures can be suppressed by only one 0.5 s electrical stimulation.

A closed-loop brain computer interface for real-time seizure detection and control

The worldwide prevalence of epilepsy is approximately 1%, and 25% of epilepsy patients cannot be treated sufficiently by available therapies. Brain stimulation with closed-loop seizure control has recently been proposed as an innovative and effective alternative. In this paper, a portable closed-loop brain computer interface for seizure control was developed and shown with several aspects of advantages, including high seizure detection rate (92–99% during wake-sleep states), low false detection rate (1.2–2.5%), and small size. The seizure detection and electrical stimulation latency was not greater than 0.6 s after seizure onset. A wireless communication feature also provided flexibility for subjects freeing from the hassle of wires. Experimental data from freely moving rats supported the functional possibility of a real-time closed-loop seizure controller.

EJVM: an economic Java run-time environment for embedded devices

As network‐enabled embedded devices and Java grow in their popularity, embedded system researchers start seeking ways to make these devices Java‐enabled. However, it is a challenge to apply Java technology to these devices due to their shortage of resources.

Design and Implementation of a Modularized Polysomnography System

In recent years, an increasing number of people suffer from sleep disorders. Polysomnography (PSG) is commonly used in hospitals or sleep centers to diagnose sleep disorders because it continuously and simultaneously records multiple physiological signals during sleep. However, the excessive number of wired connections for conventional PSG is often a problem that leads to sleep disturbance. Due to the high cost and bulky body, traditional PSG systems are not suitable for sleep recording at home. This paper proposes the design and implementation of a modularized and distributed PSG system that is more convenient and has potential for recording at home. It is composed of multiple, tiny, low-cost, and wireless-synchronized signal acquisition nodes, and each node acquires specific physiological signals within a small body region to reduce sleep disturbance as a result of recording wires. To evaluate accuracy, the system and a commercial PSG system were mounted on subjects to simultaneously perform overnight recording, and the recorded data were compared. A two-phase sleep experiment was also performed to compare the comfortableness of these two systems. The results show that, in addition to high consistency (>; 93%) with the reference system, due to the reduction of the disturbance from recording wires, the proposed system has better comfortableness performance in terms of several objective and subjective sleep indices.

A Versatile Wireless Portable Monitoring System for Brain–Behavior Approaches

It is critical to set up a precise and feasible monitoring system for a variety of animal and human studies. A multichannel wireless system for monitoring physiological signals of freely moving rats is presented. This system combines electroencephalogram (EEG) and acceleration signals, enabling the study of association between brain and behavior. A combination of EEG and accelerometers eliminates the necessity for complicated video installation as well as time-consuming and tedious analysis of recorded videos. The IEEE 802.15.4 based wireless communication frees the experimental subject from the hassle of wires and reduces wire artifacts during recording. Long-period continuous recording was possible because of the low power feature of the system. Methods for automatic wake-sleep state discrimination and temporal lobe epileptic seizure detection are also proposed to demonstrate the advantages of the system. An accuracy of up to 96.22% for the automatic discrimination of wake-sleep states is an advantage of our system. In addition, the detection of amygdala-kindling temporal lobe seizures reaches 100% with zero false alarms, greatly saving manpower in the identification of temporal lobe epilepsy.

CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management

Scratchpad memory (SPM) has been increasingly used in embedded systems due to its higher efficiency in terms of energy and area compared to that of ordinary cache. A hybrid on-chip memory architecture that combines SPM with a mini-cache has been proposed. One key issue for hybrid on-chip memory architectures is to reduce the number of off-chip memory accesses and energy consumption. Existing methods achieve this by moving the most frequently accessed data into SPM. However, these methods may be ineffective because the main source of off-chip memory accesses may not be the most frequently accessed data. Instead, most off-chip memory accesses are caused by cache misses, so reducing the latter will reduce the former. Cache misses are mainly caused by data contending for cache lines. Therefore, this paper proposes a contention-aware SPM allocation method for hybrid on-chip management. The number of cache misses for a page is used as a metric to determine whether a page should be moved to SPM. When the number of misses for a page exceeds a threshold, the page is moved to SPM, reducing cache contention. Experimental results show that the proposed method can reduce the energy delay product by 35% to 53% compared to a cache-only on-chip memory architecture and 19% to 31% compared to an existing hybrid on-chip memory architecture.

BLAS: Block-level adaptive striping for solid-state drives

Increasing the degree of parallelism and reducing the overhead of garbage collection (GC overhead) are the two keys to enhancing the performance of solid-state drives (SSDs). SSDs employ multichannel architectures, and a data placement scheme in an SSD determines how the data are striped to the channels. Without considering the data access pattern, existing fixed and device-level data placement schemes may have either high GC overhead or poor I/O parallelism, resulting in degraded performance. In this article, an adaptive block-level data placement scheme called BLAS is proposed to maximize the I/O parallelism while simultaneously minimizing the GC overhead. In contrast to existing device-level schemes, BLAS allows different data placement policies for blocks with different access patterns. Pages in read-intensive blocks are scattered over various channels to maximize the degree of read parallelism, while pages in each of the remaining blocks are attempted to be gathered in the same physical block to minimize the GC overhead. Moreover, BLAS allows the placement policy for a logical block to be changed dynamically according to the access pattern changes of that block. Finally, a parallelism-aware write buffer management approach is adopted in BLAS to maximize the degree of write parallelism. Performance results show that BLAS yields a significant improvement in the SSD response time when compared to existing device-level schemes. In particular, BLAS outperforms device-level page striping and device-level block striping by factors of up to 8.75 and 7.41, respectively. Moreover, BLAS achieves low GC overhead and is effective in adapting to workload changes.

Building Multi-kernel Embedded System on PAC Multi-core Platform

It is common nowadays that consumer embedded system products are built on platforms with System-On-a-Chip (SOC) in which two or more processor cores, which are not necessarily of the same type, are put into a single chip and form the architecture of Chip-level Multi-Processor (CMP). Although such platform is capable of achieving high performance at relatively low cost, the system architecture of CMP brings new design challenges as well as increased complexity in developing embedded software especially at the level of kernel or operating system software. This paper presents our experience and some preliminary results from the project of building a multi-kernel embedded system platform for application software running in the environment of a newly developed multi-core SOC, namely PAC Duo SOC, which is the latest product from the PAC (short for Parallel Architecture Core) Project initiated by the Industry Technology Research Institute (ITRI) in Taiwan. PAC Duo SOC is a chip-level heterogeneous multi-processor SOC composed of one ARM926 core serving as the general purpose processor (GPP for short) and two ITRI PAC DSP cores serving as the special purpose processors (SPP). We ported Linux operating system to run on the ARM926 processor and ported mC/OS-II real-time kernel to run on one PAC DSP core, leaving the other PAC DSP core with the option, for flexibility, of running either mC/OS-II or a different kernel. In addition, an inter-processor communication (IPC) mechanism is developed which not only takes application-specific requirements into account but also takes advantages of hardware features.