Dafang Zhang

A Fault-Tolerant Watermarking Algorithm for FPGA IP Protection

Intellectual Property (IP) is difficult to identify when the watermarks are impaired in previous work. To address this issue, we propose a fault-tolerant watermarking scheme for FPGA IP design. The scheme employs Blakley threshold method for signature sharing. The watermarks are then encoded with Reed-Solomon (RS) coding and finally embedded into unused LUTs of used slice. The signature sharing makes it unnecessary to extract all embedded watermarks in authentication. The complete signature can be retrieved with several watermarks even if other watermarks are damaged. The experiments show that the fault-tolerant scheme incurs no extra resource and timing overhead and has good robustness against removal attacks.

Signature Restoration for Enhancing Robustness of FPGA IP Designs

Many watermarking techniques for intellectual property IP protection are not resilient to tampering or removal attacks, especially for field programmable gate array FPGA-based IP cores. If attacked, the damaged watermarks cannot provide sufficient evidence in front of a court. To address this issue, the authors present a signature restoration scheme. The thought of secret sharing is introduced to share the signature into small watermarks. These watermarks are encoded with Reed-Solomon RS codes and embedded into unused lookup tables LUTs of used slices. Unlike most of existing techniques, the proposed scheme can restore the signature only by extracting parts of watermarks. So, it is tolerant to some damaged watermarks caused by removal attacks. The experiments show that the proposed scheme incurs no extra hardware resource and timing overhead. The robustness against attacks is much better by comparing to other schemes.

Study on IP Protection Techniques for Integrated Circuit in IOT Environment

The growth of electronic chip technique has led to frequent occurrence of intellectual property (IP) disputes. It seriously affects rapid and healthy development of semiconductor industry. To address the disputes, many IP protection methods are proposed in these years, such as IP watermarking. It is a novel technique to hide secrets in IP core to prove original ownership. This chapter focuses on two issues: how to hide secrets in IP circuit and how to authenticate IP ownership. Four types of IP watermarking methods will be concretely introduced in this chapter. (1) FPGA based IP watermarking technique. (2) FSM based IP watermarking technique. (3) DFT based IP watermarking technique. (4) Self-recoverable dual IP watermarking technique. The experiments show that the proposed schemes have low resource overhead by comparing with other schemes. Meanwhile the resistance to attacks of the watermark is encouraging as well.

NIWAS: A non-interactive watermark authentication scheme for industrial field-programmable gate array designs

Except the network attacks, the industrial networked devices in Internet of things are also threatened by intellectual property infringement. Watermarking technique is a prevalent way to avoid this threat. Previous work on authenticating a watermark in industrial intellectual properties easily discloses sensitive information of real embedded watermarks. In this case, the evidence of identifying the ownership of industrial intellectual property may be attacked by the illegal verifiers. Although several watermark detection techniques can address the disclosure of sensitive information in detection procedure, the efficiency of detection is relatively low. Besides, it may yield large communication overhead of multiple authentication rounds. Motivated by the needs of robustness and efficiency, this work proposed a zero-knowledge approach to authenticate ownership of field-programmable gate array intellectual property design in industrial environment, named NIWAS. The prover can convince the verifier that he knows a secret in the suspected intellectual property design via only one interaction. Real locations of watermarks are concealed through location obfuscation. With the received authentication package from the prover, the verifier cannot obtain other useful information about the watermarks. The experiments show that NIWAS achieves high efficiency and robustness of watermark detection.

A Novel Secure Coding-Based Approach for Multi-cast Transmission

A lot of research shows that network coding can significantly improve the performance of multi-cast transmission. However, due to the inherent disadvantage of network coding, it is very vulnerable to pollution attacks in which adversaries can inject bogus data. Moreover, those bogus data will be used with legitimate data at the downstream nodes, resulting in the failure of decoding original data as well as a sharp decrease of the network performance. In this paper, we propose a novel approach to identify pollution attacks, so that malicious nodes can be rapidly identified and isolated from the networks. In our scheme, in order to prevent malicious attacks, we design a secure infrastructure in which we exploit key pre-distribution and Message Authentication Codes(MACs), Meanwhile, we propose a secure transmission protocol. Each node registers a key from center server and appends MACs to each packet. Furthermore, in order to make verification, each node needs to carry out hash computation for every incoming packet under the secure transmission protocol. Experimental results demonstrate that our scheme has practical advantages in the presence of end-to-end delay, network throughput and identification delay.

From GPU to FPGA: A Pipelined Hierarchical Approach to Fast and Memory-Efficient NDN Name Lookup

Named Data Networking (NDN) is an emerging future Internet architecture with an alternative communication paradigm. For NDN, name lookup, just like IP address lookup for TCP/IP, plays an important role in forwarding. However, performing Longest Prefix Matching (LPM) to NDN names is more challenging. Recently, Graphic Processing Units (GPUs) have been shown to be of value in supporting wire speed name lookup [1], but the latency resulted by batching and transferring names is not so encouraging. On the other hand, in the area of IP address lookup, FPGA is widely used to implement Static Radom Accessing Memory (SRAM)-based pipeline for fast lookup and controllable latency. Thus, in this paper, we study how to accelerate NDN name lookup using FPGA-based pipeline.Data-intensive applications have become increasingly important in recent years, yet traditional data movement approaches for scientific computation are not well suited for such applications. The Active Message (AM) model is an alternative communication paradigm that is better suited for such applications by allowing computation to be dynamically moved closer to data. Given the wide usage of MPI in scientific computing, enabling an MPI-interoperable AM paradigm would allow traditional applications to incrementally start utilizing AMs in portions of their applications, thus eliminating the programming effort of rewriting entire applications. In our previous work, we extended the MPI ACCUMULATE and MPI GET ACCUMULATE operations in the MPI standard to support AMs. However, the semantics of accumulate-style AMs are fundamentally restricted by the semantics of MPI ACCUMULATE and MPI GET ACCUMULATE, which were not designed to support the AM model. In this paper, we present a new generalized framework for MPI-interoperable AMs that can alleviate those restrictions, thus providing a richer semantics to accommodate a wide variety of application computational patterns. Together with a new API, we present a detailed description of the correctness semantics of this functionality and a reference implementation that demonstrates how various API choices affect the flexibility provided to the MPI implementation and consequently its performance.As Cloud Computing becomes popular, most data owners want to outsource their data into the cloud. For security, the data needs to be encrypted. However, traditional encryption schemes obsolete most applications over encrypted data such as data searching. One solution is searchable encryption which allows a client to search over encrypted data. One hand, many researchers focus on exact searchable encryption schemes. Approximate search, on the other hand, is more practical since it allows minor typos in query words. In this paper, we present a new efficient and secure scheme to support approximate search. The main idea is to reduce the edit distance between two keywords to Hamming distance between their Bloom filters using the technique of VGRAM. To the best of our knowledge, our scheme is the first to utilize the VGRAM technique into searchable encryption. Our experiments show that the new scheme is more efficient than previous approximate searchable schemes especially in term of storage.Design knowledge is very useful in space product design tasks. In this paper, the knowledge representation and reuse technology of space product design knowledge is studied, and a new case-based knowledge reuse method is presented. In the method, the case retrieval strategy that adopts the similarity-based case retrieval algorithm based on a new model is proposed. This new multilevel case model in which mapping relationship and multiple tree are the characters is constructed by analyzing the process of space product design based on the process of rocket design. Finally, the proposed method and algorithm are verified by applying to the rocket design as an example. It is shown that the new method improves the efficiency of utilization of the design knowledge in the rocket design.

Accelerate NDN name lookup using FPGA: Challenges and a scalable approach

Recently, Graphic Processing Units (GPUs) have been shown to be of value in supporting wire-speed name lookup in Named Data Networking (NDN). However, due to the computing model on GPU, the lookup latency is not so encouraging. In this paper, we shift the focus from GPU to Field-Programmable Gate Arrays (FPGA). We highlight three key challenges in accelerating name lookup using FPGA, and then present a scalable approach to address them. In our approach, a hierarchical and compact data structure is proposed to represent the name trie, which achieves not only effective pipeline mapping but also high memory efficiency. Further, it is finally implemented as a linear pipeline on the FPGA platform, enabling both fast lookup speed and low lookup latency. The experimental results show that our approach gains a reduction of memory cost over 90% compared with the referred GPU-based solution. Besides, the lookup throughput of our approach is almost 2.4 times higher, and the latency is up to 3 orders of magnitude lower.

An IP Protection Algorithm by Watermarking Multiple Scan Chains Based on Minimum Correlation Degree of Vectors

With the rapid development of deep sub-micron integrated circuit systems, existing Intellectual Property (IP) watermarking methods for scan chains are mainly implemented by reordering and reconstructing scan chain for protecting reused IP cores. These methods may cause high vector correlation of IP watermark, which will seriously affect overhead and reliability. A multiple scan chains-based IP protection method with minimum test vectors was proposed in this paper. Firstly, the test vector sequence for scan input was generated by the generator of pseudo-random test vector, then the multiple scan chains-based watermarking structure with minimum correlation degree of vectors were constructed by combining the generated sequence with the circuit-under-test. By adding constraints in the structure, watermark would be restricted to positions of certain scan cells. Finally, the watermark was inserted and extracted by altering states of specific registers in scan cells with the designed logic circuit for bit alteration. With no influence on normal circuit function, the proposed algorithm could embed and extract the information of the users legitimate ownership and effectively address high power overhead and low security. The experiments were conducted on ISCAS-89 benchmarks. The results showed that the resource overhead in watermark embedding was reduced by more than 8% under the condition of adding constraints.