Daisuke Muto

Step-Bunching Free and 30 μm-Thick SiC Epitaxial Layer Growth on 150 mm SiC Substrate

The production of 150 mm-diameter SiC epi-wafers is the key to the spread of SiC power devices. Besides, step-bunching free surface leads to high-performance devices. We have developed the production technology of the epitaxial growth with smooth surface morphology for 4º off Si-face 4H-SiC epitaxial layers on 150 mm diameter substrates. The various area observations of the surface by optical surface analyzer, confocal microscope and atomic force microscope revealed that there was no conventional step-bunching in whole wafer surface. While creating step-bunching free surface is more difficult for thicker epilayer growth, we have achieved step-bunching free surface for 30-μm thick epilayer on a 150 mm diameter substrate. The typical values of thickness uniformity of the 30μm-thick epilayer are 0.5% (σ/mean) and 1.7% (range/mean). A few interfacial dislocations (IDs) were detected for the 150 mm-diameter epi-wafer by reflection X-ray topography. We have succeeded in removal of IDs by the optimized growth condition.

Characterization of Triangular-Defects in 4° off 4H-SiC Epitaxial Wafers by Synchrotron X-Ray Topography and by Transmission Electron Microscopy

We report our investigation results on triangular-defects formed on 4deg. off 4H-SiC epi- taxial wafers. Triangular-defects that had neither down-falls nor basal-plane dislocations previously reported as origins of triangular-defects at the tips of triangle were investigated by TEM. Our TEM results revealed that foreign materials contamination that were different from well-known down- -falls in size and in composition caused one of the defect formations and abnormal domain forma- tions were implied to occur and thought to relate to defect formations. We also report that several types of microstructure existed in the isosceles of defect during dislocation analyses around triangular-defects by X-ray topography.

4H-SiC Epitaxial Growth on C-Face 150 mm SiC Substrate

The production of 150 mm-diameter SiC epitaxial wafers is the key to the spread of SiC power devices. We have developed production technology of the epitaxial growth for 4° off Carbon face (C-face) 4H-SiC epitaxial layers on 150 mm diameter substrates. Several growth parameters and hardware were optimized to obtain high uniformity wafers. We have succeeded in fabricating high quality C-face wafers with smooth surface and high uniformity.

Short-Length Step Morphology on 4° Off Si-Face Epitaxial Surface Grown on 4H-SiC Substrate

We developed a production technology for epitaxial growth with a smooth surface morphology for 4º off Si-face 4H-SiC epitaxial layers on 100 mm-diameter substrates. High-contrast topography images by optical surface analyzer revealed that a step bunching free surface was obtained throughout the whole area of the wafer surface. However, short-length steps still remained locally on the epitaxial surfaces. Using photoluminescence imaging, it was clarified that the short-length steps were morphological in nature and did not contain stacking faults. The short-length steps were generated by step-flow growth pinning caused by the shallow pits of threading screw dislocations revealed by molten KOH etching.

Investigation of carrot reduction effect on 4H-silicon carbide epitaxial wafers with optimized buffer layer

We investigated the carrot-defect reduction effect by optimizing the buffer layers of 4H-Silion Carbide (SiC) epitaxial wafers. The SiC epitaxial wafer with the 0.5 μm-thick optimized condition-B buffer layer show the carrot-defect density of 0.13 cm-2, since that with the conventional-A buffer layer were 0.68 cm-2. Although the average bunching length with the optimized condition-B buffer layer was 7-times longer than those with the conventional condition-A buffer layer, we could reduce the bunching length by applying the optimized condition-B only to the initial 0.05 μm-thick buffer layer. Finally, with the initial 0.05 μm-thick optimized condition-B buffer layers, we could achieve the SiC epitaxial wafers with only half the carrot-defect densities of those with the conventional condition-A buffer layers, while the average bunching lengths were less than 100 μm. With this condition, we could achieve the estimated yield of 90.1% with 4 x 4 mm chips, while that with the conventional condition-A buffer layer was 81.9%.

Improvement on 150 mm 4H-SiC Epitaxial Wafer Quality

For the popularization of SiC power device, improvement on both productivity and quality of 150 mm diameter SiC epitaxial wafer is inevitable. With highly productive 8x150-mm CVD reactor, we have grown epitaxial layer on 4° off 4H-SiC wafer Si-and C-face. Modifying some reactor parts and optimizing growth conditions enabled us to achieve a good balance between high uniformity and smooth surface.