Dalenda Ben Issa

A 4GHz temperature compensated CMOS ring oscillator for impulse radio UWB

This paper presents a voltage controlled ring oscillator (VCO) with a simpler temperature compensation circuit to produce a stable 4 GHz oscillation frequency. The proposed temperature compensation circuit is able to achieve a 89.25 % reduction in the variation of the center frequency of the uncompensated VCO and 108 ppm/°C temperature stability. Simulations using TSMC 0.18 µm CMOS technology show a low phase noise of a −74.55 dBc/Hz at 1 MHz offset from the carrier and a total power consumption of 11.06 mA. Therefore, the proposed oscillator system is suitable for the impulse radio ultra wide band (IR-UWB) wireless communication system.

New design of 3–10 GHz low noise amplifier for UWB receivers

In the ultra-wideband (UWB) communication system receiver, the low noise amplifier (LNA) is the critical module. The LNA is used to amplify the received signal with sufficient gain and as little additional noise as possible. This paper presents a new 3.1-10.6 GHz LNA UWB receivers. The UWB LNA was formed by two stages. The first one uses the resistive current reuse and degenerative parallel LC to provide the input matching over a wideband. The proposed UWB LNA uses an inductive-series peaking technique with cascode common-source amplifier to improve the gain, fatness and consume lower power. This LNA is designed using 0.18 μm CMOS technology. Our finding show that, the low noise amplifier LNA using these techniques allowed us to achieve a maximum power gain of 20.62 dB, a good input/output impedance matching, S11 below -10 dB and S22 below -10dB and an excellent noise figure NF between 1.6-2.5 dB.

Design and Optimization of Differential Ring Oscillator for IR-UWB Applications in 0.18 μm CMOS Technology

This study presents a two-stage ring voltage-controlled oscillator (VCO) for use in impulse-radio ultra-wideband (IR-UWB) applications. A systematic and efficient graphical optimization method was employed to find the optimal dimensions of the VCO which give a best performance. A good agreement was observed between the desired specifications and simulation results with regard to the optimum component size of the VCO circuit. The operation range of the VCO was extended to cover an ultra-wide tuning range of 176.6%. The phase noise was −107.1dBc/Hz at 10MHz offset frequency from a carrier frequency of 4GHz. The power consumption of VCO was 7.41mW from a 1.8V supply voltage. A large tuning range, low power, and appropriate phase noise were obtained with the optimum components size obtained through the optimization method.

Reconfigurable circuits design based on DG-CNTFET transistors

Controllable-polarity transistors have an interesting property, they can switch from p- to n-type behavior and vice-versa dynamically. This opens up the opportunity for building novel and complex functions in fine-grain reconfigurable logic inaccessible to MOSFETs. Double-gate carbon nanotube field effect transistors (DG-CNTFETs) is one of the major promising candidate for reconfigurable circuit reaching a good performance levels. In this paper we will demonstrate the benefit of designing a reconfigurable circuit based on a compact physical model of these transistor. First, an overview of different types of carbon nanotube field-effect, transistor (CNTFET) is given. DG-CNTFET model is described, and characterization of transistor is done. Finally a dynamically reconfigurable 8-function logic gate (CNT-DR8F) based on a (DG-CNTFET) is described, simulated and analyzed.

A 0.35 µm CMOS LC-tank injection-locked frequency divider

A divide-by-2 injection-locked frequency divider (ILFD) has been designed in a 0.35 µm CMOS process. The ILFD circuit is realized with a differential CMOS LC-tank oscillator with an injection MOS. Simulation results show that at the supply voltage of 2.5 V and by tuning Vtune from 0 to 2.5 V, the tuning range of the free-running ILFD is from 1.84 to 2.89 GHz. At the injection signal power of 0 dBm, the locking range of the proposed ILFD is about 2.49 GHz from the incident frequency 3.53 to 6.02 GHz. The ILFD dissipate 3.43 mW. At the tuning voltage of 1.6 V the simulated phase noise of the free running ILFD is −125.6 dBc/Hz at 1.066 MHz offset frequency at 2.65 GHz and the phase noise of the locked output is −132.7 dBc/Hz while the phase noise of the injected signal is −126.7 dBc/Hz.

Design nd optimization of up-conversion CMOS mixer for UWB application

A graphical optimization method optimize the CMOS Mixer is presented in this paper. The design constraints equations of gain conversion, noise figure, power consumption and IIP3 are presented in the same plane to find the optimal sizing of all components of CMOS mixer. The results show the sizing of components of up-conversion mixer and the optimal trade-off curve between high gain conversion and minimum figure noise. Simulated results and the theory results of optimization are similar; the up-conversion mixer presents gain conversion of 11.7 dB, IIP3 of 6.5dBm and figure noise of 8.8 dB. The total power consumption is 15 mW.

Graphical optimization of 4GHz CMOS LC_VCO

This paper presents graphical optimization method of LC voltage controlled oscillator (LC_VCO). This method accomplishes with optimum size of LC_VCO components. This oscillator is characterized by tuning range of 4% from carrier frequency centered in 4GHz. The phase noise is -126dBc/Hz at 1MHz offset frequency from carrier frequency of 4GHz and the power consumption is 11.6mW from a 2.5V supply voltage. Theory approximations by graphical optimization method are verified by simulation.

An UWB pulse generator using switching CMOS active inductor oscillator

A novel design of an Ultra Wide Band (UWB) pulse generator is presented. This topology is based on the switching of a CMOS active inductor oscillator. With the agreement of the desired specifications, the design technique of UWB pulse generator is described in this work. The achieved simulated results show the best performances of the proposed UWB pulse generator in terms of power consumption (22.6mW at 1.8V voltage supply), frequency bandwidth (530MHz), power spectral density (PSD) which is limited to -43.1dBm/MHz and the best agreement in Federal Communication Commission (FCC). This UWB pulse generator is implemented in a 0.18 μm CMOS process technology.

Low noise amplifier for MB-OFDM UWB receivers

This paper presented a reconfigurable low noise amplifier (LNA) design. This circuit is the most critical block in a multi-band Ultra Wide Band (UWB) receiver architectures. The proposed LNA is composed of three stages. The first one is a common source (CS) stage. Its objective is to provide a good input reflection coefficient S11 and a low noise figure. The second stage composed of a programmable circuit to select the operation band. A current reuse technique is used in the third stage to achieve a high gain and low power consumption. The proposed multi-band LNA operates in 3 sub bands of Multi Band Orthogonal Frequency Division Multiplexing (MB-OFDM) of 500 MHz, centered at 3.5, 4, 4.5 GHz frequencies. The simulated results of the designed LNA show an average power gain up to 28 dB, 25 dB, 27 dB for band 1, band 2 and band 3, respectively. At a voltage supply equal to 1V, The LNA consumes only 3.4mW. This circuit is designed in CMOS 0.18 μm technology.

Graphical optimization method applied to a 6 GHz single-ended ring oscillators

In this paper, we present a graphical optimization method in order to optimize the CMOS Ring oscillators. The design constraints equations of phase noise, tuning range, power consumption and start-up condition are presented in the same plan to find the optimal sizing of all components of CMOS ring oscillators. The optimized ring oscillator characteristics a simulated phase noise of -111.25dBc/Hz at 10 MHz offset from a 6 GHz. The VCO turns from 7.74 GHz to 4.26 GHz with a tuning voltage that varies from 0.5 V to 1.4 V, and the designed oscillator dissipates only 7 mW at 6 GHz carrier. Simulation verifies the theory approximations done by the graphical optimization method.