Dan Perry

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 ) and power (3%) overhead.

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single- and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.

Test structures for characterization of through silicon vias

As silicon technology reaches extreme sub-um dimensions, the industry has reached for “more than Moore” solutions to enable advancements in integration, lower system cost, and improve packaging footprints. Probably the best known of the more-than-Moore solutions is 3D chip stacking using through silicon vias (TSVs). This technology requires accurate characterization of the TSV, the thinned silicon, and the stacked die. Our paper deals with TSV characterization by means of specially designed test structures.

Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting materials. The impact of wafer thinning and of the proximity of through silicon via on active devices, back end structures, ring oscillators and mixed signal circuit are reported for the first time for a High-k/Metal Gate first strained CMOS technology with low-k BEOL. The relative stress induced by the STI and the TSV are measured by micro-Raman spectroscopy. The measured impact of the stress on a sensitive DAC circuit is used to define a safe keep out area.

Test structures for characterization of thermal-mechanical stress in 3D stacked IC for analog design

In this paper we present test structures and measurement techniques that enable extraction of significance of effects expected in 3D TSV technologies. The DAC test structure is optimized to detect Ion changes down to 0.5 % due to TSV proximity, TSV orientation, thermal hotspots and wafer thinning/stacking process. The results obtained from the stand-alone MOS devices and the DAC structure clearly indicate the impact of TSV proximity and TSV orientation on the carrier mobility of nearby transistors.

Test Structures for Characterization of Through-Silicon Vias

3-D chip stacking using through-silicon vias (TSVs) requires accurate characterization of the TSV, the thinned silicon, and the stacked dies. This paper proposes a set of test structures specifically designed to address the electrical characterization of TSV in terms of resistance, capacitance, leakage, yield, and their impact on the 2-D interconnects of the stacked dies. Examples of the use of these structures are presented, and the observed electrical behaviors are explained with the support of FIB cross-section images.

Design for manufacturability for fabless manufactuers

When a company designs and sells ICs but outsources their manufacture, design for manufacturability poses special challenges. It is clear that these DfM solutions are very complex and require a series of fundamental new physical models and design practices. Practical deployment of DfM solutions requires development of an entire incremental infrastructure on both the process and design sides of the technology integration spectrum. Optimizing the various DfM methods involves complex, multi-faceted tradeoffs that are ultimately dependent on target technology and various product attributes. DfM is definitely not a one-size-fits-all panacea for all of the process manufacturability and variability challenges. Complete and successful DfM deployment is a true ecosystem that requires multiple tools using multiple models, potentially calibrated to multiple levels of accuracy, inserted at multiple points in the design flow.

Design of Test Structures for the Characterization of Thermal–Mechanical Stress in 3D-Stacked IC

In this paper, we present test structures and measurement techniques that enable the extraction of the significance of the thermal-mechanical stress in 3D-stacked integrated circuit technology. Heaters and integrated diodes have been used to determine the impact of hotspots in 3-D systems. The results obtained showed that in 3-D case, the peak temperature of a hotspot is three times higher compared to a traditional 2-D system. For the characterization of through silicon vias (TSVs)-induced stress and its impact on analog metal-oxide semiconductor (MOS) devices, a 10-bit current steering digital-to-analog converter (DAC) test structure is utilized. The DAC has been optimized to detect ion changes down to 0.5% due to TSV proximity, TSV orientation, thermal hotspots, and wafer thinning or stacking process. The results obtained from stand-alone short-channel MOS devices and the DAC structure clearly indicate the impact of TSV proximity and TSV orientation on the carrier mobility of nearby transistors.

An efficient array structure to characterize the impact of through silicon vias on FET devices

We present a test structure to measure the impact of 3D processing, especially through silicon vias, on FET devices. We also show proven techniques for enabling large numbers of devices to be accessed from a limited number of pads. We will show that through silicon via (TSV) proximity and FET channel length impact the devices behavior. We will show behavior can be predicted by symmetry. Through measurement, analsysis, and correlation with mechanical stress models, we demonstrate that our structure can predict how FET devices will behave in 3D stacked products.

Chip Package Interaction with fine pitch Cu pillar bump using mass reflow and thermal compression bonding assembly process for 20nm/16nm and beyond

This paper summarizes key learnings on 20/16nm CPI (Chip-Package-Interaction) challenges at 100um pitch and below to support ever increasing performance/cost/form factor demands for high performance mobile SoCs. CPI solutions for two types of Cu pillar interconnects using mass reflow and thermal compression type assembly process respectively are studied in technology development/production, and separate bump cell structures are proposed.