Dana How

BiNMOS: a basic cell for BiCMOS sea-of-gates

A BiNMOS test chip has been designed and fabricated in 0.8-μm BiCMOS technology. The test chip consists of a 4×22 array of BiNMOS cells. The test structures include a ring oscillator, a 4-bit SRAM (static random-access memory) core, five types of buffers, a MUX, and a shift register. Ring oscillator measurements indicate a basic BiNMOS inverter delay of 240 ps (FO=1), a result that agrees well with simulation

Field Programmable MCM Systems Design Of An Interconnection Frame

We present a new field programmable architecture for prototyping large designs using multiple FPGAs which offers excellent performance and economy while retaining the immediate turnaround of FPGAs a t the system level. For our packaging technology we have selected MCMs[l] because they offer the large pin count per chip necessary for high chip utilization in a partitioned design, and because the off chip delays are smaller than with PCBs. Due to the technological complexities of providing configurability a t the MCM level we assume a fixed, nonconfigurable, statisticallydetermined wiring pattern. It would be convenient to use commercially available FPGAs (e.g. Actel[4] and Xilinx[5]), but these are not suited to our requirements. First, such FPGAs do not provide the high pin to gate ratio required when partitioning a design among multiple FPGAs. As a result the FPGAs are typically underutilized[6]. Secondly, since the 1/0 buffers of these chips are designed for general purpose use with PCBs, they do not give the better performance possible with MCMs. Responding to these two considerations, we could use an FPGA with a commercial internal architecture, yet with a high pin count and special 1/0 buffers. However, the fixed MCM wiring pattern assumed in our architecture imposes severe routing constraints which we solve by routing many signals through the FPGAs themselves[6]. Since the routing architectures of commercial FPGAs are optimized for local intercon-

Peripheral circuit design for field programmable MCM systems

A field programmable multichip module (MCM) architecture utilizing an array of modified field-programmable gate arrays (FPGAs) is proposed. Interconnections are provided by a fixed wiring network on the MCM, and by programmable interconnection frames on each FPGA. It is shown that full-swing CMOS peripheral circuits are faster than low-swing CMOS circuits. Buffering configurations for the interconnection frame which exploit the MCM performance benefits were selected and optimized. Bidirectional bus implementations using the frame are presented.<<ETX>>